The researchers have increased the speed of an algorithm known as the fast Fourier transform (FFT) – which is used in spectral analysis, radar technology and telecommunication – by mapping the pipeline single-path delay feedback FFT architecture.
"Until now, people have believed that once an FPGA is full it cannot accommodate any more. If you want new functionality in this case, you have to completely rebuild the hardware, which is expensive," said senior lecturer Oscar Gustafsson.
"This advance will save huge sums for demanding calculations in industry, and will make it possible to implement new functionality without needing to replace the hardware.”
The method is based on ensuring that the signal takes a smarter route through the various building blocks inside the chip.
"Normally, you choose an algorithm that can carry out the desired calculations, and then build up the structure, the architecture, using the required blocks. This is then transferred to the FPGA,” PhD student Carl Ingemarsson explained.
“But we have also looked at how the logic is built up, the routes the signals take, and what happens to them inside the chip. We have then adapted the architecture and the mapping onto the chip using the results of this analysis."
According to the researchers, the result is that the FPGAs can be made to work five times as fast or to deal with five times the number of calculations. The results show that the FPGA mapping is crucial – not only the architecture and algorithm choices.
"It should be possible to automate this optimisation of the chip," Ingemarsson concluded.