According to the company, SYZYGY is intended to satisfy the need for a compact, low cost, low pin-count, high performance connectivity solution between FPGAs and single-purpose hardware peripherals. Potential applications include devices for high speed data acquisition, digital image capture, software-defined radio, and digital communication.
“SYZYGY is intended to fit the sweet spot of peripheral connectivity between the existing low-performance, low pin-count PMOD and the expensive, high-performance ultra-high pin-count of FMC,” said Jake Janovetz, president of Opal Kelly.
“We envision SYZYGY occupying the space between present standards where pin economy, low cost, and high performance converge. Carriers could offer multiple connectivity options to provide additional flexibility to system implementers.”
The SYZYGY specification defines two connector types: Standard and Transceiver. The Standard SYZYGY connector offers up to 28 single-ended, impedance-controlled signals, 16 of which may be defined as differential pairs for interface standards such as LVDS.
The Transceiver SYZYGY connector features four lanes of Gigabit-class transceiver connections and also offers up to 18 single-ended signals. The Transceiver connector is intended for use with JESD204B data acquisition, SFP+ transceivers, and other devices requiring high speed SERDES.
Both Standard and Transceiver connectors have optional low cost, high performance coaxial or twin axial cable assemblies.
Designed to accommodate the wide range of I/O voltages common with FPGA systems, SYZYGY defines SYZYGY DNA and SmartVIO. SYZYGY DNA is said to be simple way for peripherals to communicate personality data such as manufacturer name, product name, and serial number to the carrier.
SmartVIO is included in the DNA payload and defines the range of I/O voltages acceptable to the peripheral so that carriers can set I/O voltages accordingly.
In addition to the specification, Opal Kelly will release a SYZYGYTM compatible carrier – the Hub – an open-source board incorporating a Xilinx Zynq SoC FPGA.