CMOS research reveals advances in sub micron scaling for logic and memory

One device, based on nonsilicon channels, is said to scale high performance logic towards the sub20nm node. Imec has also developed low leakage capacitors, allowing dram to be pushed to the 2x nm node. And, says the Belgian research centre, the switching mechanism of resistive RAM for next generation flash memories (RRAM) has been unraveled. To scale cmos towards the sub20nm node imec developed a new implant free silicon germanium (SiGe) quantum well pFET device featuring a high mobility SiGe channel with raised SiGe source/drains using bulk-Si substrates. According to imec, the high electron mobility transistor has an effective oxide thickness (eot) of 0.85 and achieves a 50% higher saturation drive current compared to Si-controlled pFETs. Imec claims the device concept is compatible with additional strain boosters paving the way to deep submicron scaling achieving high performance. Imec also reported a viable path to scale dram to the 2x node by using novel stack engineering. To achieve this, low leakage at an eot of 0.4nm and less is required, deposited with highly conformal atomic layer deposition (ald) processes for compatibility with large aspect ratio structures. The researchers have reported 'record low' leakage MIM capacitors, J_G of 10^-6 A/cm² at 0.4nm eot, enabling to scale dram to the 2x nm node. By finding synergies between conventional logic ICs and rram, imec claims to have succeeded in setting out the theory for predicting the maximum applicable V_set and revealed that the reset operation corresponds to a pinch off of the filament at its narrowest point. Imec's key partners in its core cmos programmes include Intel, Samsung, TSMC, Infineon and STMicroelectronics.