Chipmakers demand better system level support from EDA vendors

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According to speakers at the recent Design Automation Conference (DAC), a design tool gap has opened up as large chipmakers attempt to move to system-level design and to rein in ballooning compute costs.
Lisa Su, pictured, chief technology officer with Freescale, said in her keynote speech during the conference: "An SoC level tool metric that we use is being able to complete verification and validation in less than 12 hours per simulation run. It seems a good metric because of the way we run projects across global teams."

However, Su expects design sizes to soon increase to the point where, using current levels of technology, simulations would take more than 100 hours to complete. Su said software developers need much faster system level simulations to let them identify potential problems with designs before they have been fabbed. Adding his weight to Su's, Gadi Singer, vice president and general manager of Intel's SoC group, demanded the electronic design automation (EDA) sector devote more attention to system level design. He outlined a five point programme to make high level design the basis for future chip designs and to remove the need to write hardware descriptions in languages such as Verilog. Instead, a combination of high level synthesis and optimisation tools would be used to create the hardware. Small changes to the RTL code would then be reflected automatically at the system level. "I would request that the eda industry addresses that new challenge with a sense of urgency," said Singer. Meanwhile, in the midweek ESL Symposium, Jean-Marc Chateau, vice president of platforms and tools at STMicroelectronics, agreed system level simulation tools are currently not fast enough. "If you can't get speed, the software people won't use it." He added that interoperability issues are becoming big issues. "Interoperability between system level models is still not fully possible."