Cadence unveils first DDR4 IP solution

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Cadence Design Systems has announced the availability of the world's first DDR4 IP solution. According to the company it will enable SoC designers to take advantage of the performance gains available with the emerging DDR4 memory standard.

Working in conjunction with the recently acquired Denali, the platform includes hard and soft PHY IP, controller IP, memory models, verification IP, tools and methodologies and signal integrity reference designs for the package and board. "Memory management IP is central to successfully delivering differentiated products, and the quality of the IP dramatically impacts the performance, power and signal integrity of the entire SoC and system," said Vishal Kapoor, vice president of the SoC Realization Group for Cadence. "Many designers are finding it increasingly challenging to design and integrate memory management IP onto their SoCs. As the only company to support its high quality IP with an integration environment spanning every aspect of design – from silicon to package to board – we dramatically lower the risk associated with realising complex DDR4 based SoC designs." The DDR4 specification, an evolutionary SDRAM memory technology standard currently under review at JEDEC, proposes speeds ranging from 1600 mega transfers per second (MT/s) up to 3200MT/s, more than 50 % faster than the current DDR3 standard. As the standard evolves to support higher frequencies and throughput, signal integrity, power and performance issues multiply. Cadence says its integration environment enables customers to model and analyse their target memory topology, and verify the behaviour of the IP at both the SoC and system levels. The soft PHY and controller can be synthesised to support the full range of frequencies and voltages and designers can deliver either a pure DDR4 SoC, or combine DDR4 with other technologies like DDR3 or LPDDR2. The specification is expected to be finalized this year. "We expect vendors, especially in the networking and enterprise markets, to begin designing equipment utilising DDR4 in 2012," said Ganesh Ramamoorthy, principal research analyst, Gartner. "Since SoC designs start well in advance of system design, we believe the demand for DDR4 IP will begin from now on and grow strongly to reach peak demand by 2014." DDR4 controller IP, verification IP and memory models are available now, and supported by both Cadence and third party design tools and methodologies. A soft DDR4 PHY is expected to be available this quarter, while a hard PHY solution for 28nm TSMC geometries is expected to be available by Q3 2011.