ARM unveils new memory interface and next generation debug solutions
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ARM has announced the launch of its next generation system solution for debug and trace, along with its fourth generation memory interface solution.
The ARM CoreSight SoC-400 (pictured) is a configurable debug and trace solution for complex SoC designs and is designed to provide high performance in applications such as mobile phones, tablets, home, wireless infrastructure, networking and gaming. According to ARM, it delivers software developers with a powerful, modular debug and trace infrastructure, and tool chain.
"Until recently debug and trace solutions have been an afterthought in the SoC design process, as basic functionality was acceptable in less demanding applications," said Mike Dimelow, marketing director, Processor Division, ARM. "However, as multicore applications are more common place, debug and trace solutions become critical to SoC designers and software developers. CoreSight SoC-400 is already providing improved productivity for all parties involved in the design process."
ARM's memory interface solution is said to deliver 90% utilisation efficiency and targets high performance, low latency SoC applications. The interface comprises its Dynamic Memory Controller (DMC-400) and an ARM Artisan DDR PHY hard macro. According to ARM, it has been specifically designed to augment the performance of ARM Cortex-A series processors, including the Cortex-A9 and Cortex-A15 MPCore processors. This, says the company, enables the development of high bandwidth, high efficiency multicore systems. The controller and the PHY (40nm) have already been licensed by a number of major customers including LG Electronics.
The ARM CoreLink DMC-400 implements advanced memory scheduling to deliver what ARM describes as 'industry leading memory utilisation efficiency' in excess of 90% across multiple memory channels. Interfacing through a DFI 2.1 compliant PHY to DDR2, DDR3 or LPDDR2 DRAM products, it is the first memory controller designed to integrate with the AMBA 4 ACE or AMBA3 AXI3 interfaces, sharing a system wide QoS that guarantees bandwidth and latency contracts from processor though to external memory.
