Whatever happened to structured asics?

When it was first mooted as an idea, the concept of structured asics seemed very sound and promised to be the solution to a set of very significant problems. These problems had been growing in importance to the point where the number of asics being designed each year was declining drastically – and that trend is still continuing. According to Gartner Dataquest, 1996 was the best year for asic designs, with around 11,000 devices. The number of asics being designed today is less than one third of that number. However, those designs are much more expensive, which means the overall value of the asic market has not declined. What is clear is that this situation cannot continue and, with asic starts continuing to decline, the market must begin to fall. So why have asic designs starts decreased? This is fundamentally a problem of the non recurring engineering (NRE) charge, the cost that an asic designer pays to get the masks made and the first samples delivered. Back in the 1990s, typical NREs were less than $100,000 and there were a large number of designs that could deal with charges like this. If your product sells in volumes of 100,000 per year, than an NRE of $100,000 only adds $1 per part to the first year's costs. And, in the 1990s, enough products sold in sufficient volume that such an NRE was an acceptable tradeoff in order to get custom silicon optimised to the application and at a low unit price. However, modern NREs are of the order of millions of dollars and there are very few applications that run to sufficient volumes to justify such a high up front cost. A further complication is that asic manufacturers will typically not be interested in accepting such a design unless they see significant wafer volume – and, with 12in/300mm wafers becoming the norm, that means spectacular volumes of chips. With the exception of mobile phones and other handheld devices and video games, there really aren't that many designs which justify creating asics. This is why the structured asic concept sounded so good to vendors and consumers alike. From the manufacturer's perspective, it meant their engineering development would be much easier. By essentially reinventing the gate array, but with denser memories and some other embedded structure (hence the term structured asics), the manufacturer could reuse the masterslice for multiple designs, thereby amortising the development cost across multiple designs and customers. From the customer's point of view, the NRE would be much lower, as only a few masks were required to modify the metal layers and customise the design. On that basis, everyone should win! Where are they now? Jump forward a few years and where are all the structured asic designs? The majority of the companies which jumped in with early products (or at least announcements) have withdrawn from the market. LSI Logic, NEC and Fujitsu all abandoned the idea, either returning to the forms of asic they knew or leaving the market completely. None of the start up companies that were created either to address the structured asic market or who modified their business plans to adapt to it has seen significant success. Why is this? There isn't one simple reason why the structured asic hasn't broken through, but here are a few of the main culprits: * Flow issues The larger asic providers that promised to deliver structured asics typically used their existing standard cell asic back end tools and methodologies. This meant they typically had to burn a lot of engineering in order to tape out a design. This was fine when designs were very valuable and high volume. But when they weren't, it wasn't worth the asic vendor's own investment. ASIC vendors therefore quickly found that the return simply wasn't there for them to chase this kind of business. They were therefore presented with a choice: either giving up or completely reengineering a more cost and effort effective back end. They all chose to give up. * Over promising Some structured asic providers erred by promising that their flows would be significantly easier than anything that had gone before. Designers could prototype in fpgas and 'seamlessly migrate' to a structured asic without burning any of their own engineering resource. Designers who tried such flows typically found that the effort they were expected to make was far higher than they had ever expected – and they were still required to modify their fpga designs to make them more asic like, thereby removing much of the attraction in the first place. * Poor execution Some structured asic vendors found that they were hard pressed to deliver working silicon reliably. Customers, who were already concerned about giving a new company their precious designs, were understandably reluctant to go back a second time when the first didn't work as expected. They think it's all over Is the era of the structured asic over before it ever got going? It's certainly true that none of the existing vendors in the market has made a success of it. However, the reasons for the emergence of the structured asic concept have not gone away and, arguably, they are more pressing than ever. While ASIC NREs are getting increasingly unaffordable for most applications and customers, there is still a real need for hardware based differentiation when designing a system – using a microprocessor or an assp and simply differentiating in software is not enough in many markets. The market clearly wants to design using fpgas, because the approach supports ease of design, flexibility and time to market requirements. If companies are going to 'take a chance' on emerging markets, then using an fpga to test the water makes a lot of sense. However, there has to be a really easy way to get from a working fpga to a cost and power reduced asic for volume production which doesn't require the designer to design twice – once for the fpga and then for the structured asic. If someone could come out with a product that could solve these issues, there is clearly demand for it out there.