Mixed signal ASICs can prove less expensive than you might think

4 min read

ASICs, we have been told over the last few years, are the preserve of the rich. But not every ASIC has to be manufactured at the 'bleeding edge' and, for mixed signal ASICs, a convincing argument can be made that trailing edge processes are more appropriate and cost effective.

Richard Mount, sales and marketing director for Swindon Silicon Systems (SSS), said: "It's a myth that ASICs are expensive and the NRE is enormous. It's just not the case." Formed in 1978 as a design house, SSS is a specialist in the design and supply of high performance ASICs and standard parts. Part of Schrader International, it supplies more than 50% of the ASICs used in tyre pressure monitoring systems. Non-recurring engineering (NRE) is one area where costs are coming down, said Mount. "NRE has two dimensions. One is design cost. The economy has been in recession for a while and everyone is aggressive in terms of pricing. Modelling tools are also more accurate, so the amount of engineering effort needed is coming down," he noted, "particularly if there is a good design team which knows its stuff." The other contributor to NRE is subcontractor costs. "These are being driven down by customers," Mount observed. "It's getting less expensive to make ASICs, particularly if you take advantage of MPW and MLM options." MPW – multi project wafers – and MLM – multi layer mask – are ways to manage cost. "A lot of companies say they can't afford ASICs," Mount continued, "but when you talk to them, they realise they can." Mount suggests ASICs can play a role for many companies by reducing PCB component count. "Many companies face obsolescence issues with discrete components," Mount pointed out. "What can they do? We have companies with large PCBs featuring lots of discretes coming to us and asking whether we can help. The answer is 'yes' and the solution is simple." Again, Mount points to the cost of an ASIC compared to that of discretes. "When customers find out the NRE costs and unit price aren't as high as they thought, they can actually be 'gobsmacked'. They can end up with a lower overall BoM cost." One reason mixed signal ASICs can be less expensive than expected is because they are targeted at legacy processes, where costs are lower. "We target designs at 0.18 and 0.35µm CMOS and BiCMOS processes," Mount said. "You really don't have to be at the leading edge unless you want to be. It's a case by case decision because there are trade offs between size, cost and performance. "If a customer really needs low unit cost, 0.6µm technology is available, but cost would be traded against performance." SSS' preferred foundry partners are X-FAB and ams. "We have many years of experience with them," Mount said, "and a great relationship." Whilst SSS uses foundry libraries and process development kits, it also uses as much of its IP as it can. "Each design is different and we see customer IP incorporated in about 30% of them, but it does need to be reformatted to the appropriate process." SSS is also seeing a trend towards greater integration – and not just the 'obvious' elements. "Some customers are asking us whether we can include a processor in the design," Mount noted. "In fact, we are currently working on a project in which an ARM Cortex microcontroller core is being integrated into an ASIC." Does this imply the 'traditional' definition of an ASIC is changing? Are the designs being undertaken at SSS more like SoCs than ASICs? "Yes," said Mount, "because this approach is bringing more programmability, even if the design doesn't include a processor." Another ASIC 'myth' which Mount debunked is volume; you don't have to commit to vast numbers. "It's on a case by case basis and depends on the target market," Mount said. "While consumer markets are very price sensitive, the industrial sector isn't. Minimum order quantities depend on the investment we make. We set a financial target and look to reach that within a year. Every design has a ramp and we take that into account. "So long as we're covered for 25 wafers," he added, "that's fine. The customer will get about 2000 ASICs per wafer and could draw these down over two years." Mount also challenged the concept of ASIC inflexibility. "Most of the designs we do aren't 'set in stone'," he claimed. "It's all about the mask layers. We can change the metal or the poly layers, but it does depend on the volumes involved." Here, the MLM approach is preferred. "It's more flexible," Mount claimed. "MPW only runs every couple of months. If you miss it, you have to wait and you're only guaranteed 100 ASICs per wafer. "MLM is more expensive, but not that much. It's a prototype wafer approach, with four masks per reticule. We order six engineering wafers: two are taken to production and packaged; two are held at the metal stage; and the last two are held at the poly stage. "Once we are happy with the packaged parts, we have wafers waiting; there's no tape out to do and no waiting for a respin." The unused wafers are where design changes can be made. One of SSS' customers is US based microbattery specialist ZPower. Troy Renken, vice president of product planning and electronics, said: "I visited Electronica in 2012, looking for a silicon design partner who could develop a high efficiency, small form factor, specialised DC/DC converter optimised for our rechargeable silver-zinc battery chemistry. We selected SSS based on its experience with small form factor, low current, mixed signal designs and our confidence in its quality systems." What does an ASIC bring to ZPower's products? "Our battery chemistry has a higher voltage (about 400mV) than the disposable batteries typically used in existing hearing aids. The ASIC we've developed with SSS enables manufacturers to adopt our battery technology. In addition, we have plans to expand our portfolio to include a small form factor charger ASIC." The bumped die ASIC is approximately 2mm2 and requires six 0201 passives. At its heart is a specialised DC/DC converter which enables hearing aid manufacturers to avoid changes to their power section of their DSP or to firmware. In addition to the regulator, the ASIC includes a digital section for selecting output voltages and protecting the battery from over discharge. According to Renken, the previous approach used off the shelf linear regulators. "These weren't optimised for our battery chemistry. While acceptable for field testing, they were too large to be used in a production hearing aid design and didn't take full advantage of the battery's higher energy, so the delivered battery capacity wasn't maximised." SSS is changing with the market. "Mixed signal is now our forté," Mount said. "We used to be big A, small D, but we're now developing the digital design side because of the need for more integration. However, we wouldn't attempt a complete digital design." Concluding, Mount said SSS was a niche supplier because ASICs are still niche products. "But we'll double our turnover in the next three years."