Transistors are expected to cost more in the future; something Moore’s Law doesn’t prescribe

4 mins read

Silicon scaling has never been simple, but it has at least been predictable for 40 years. But forthcoming processes have changed that dramatically. Instead of being cheaper on a per-transistor basis, the 14nm and 10nm processes could be much more expensive than their predecessors unless something radical happens (see fig 1).

Chip designers have critical choices to make. They can stick with the existing processes – 28nm, for example – and hope their competitors don't jump to 14nm, where they might offer better performance for the same price or take advantage of possible future efficiencies. They can opt for the finFET-type process already in production at Intel and which should soon ramp at foundries such as Samsung Semiconductor and TSMC. Or they could pick the wild card; STMicroelectronics' fully depleted silicon on insulator (FD-SOI). Part of the problem is that 28nm LP is, considering the density that it offers, a very cost effective process. A number of microcontroller manufacturers, such as Freescale, aim to use it relatively soon. This is unusual for a market where cost pressures have tended to favour more mature processes. But memory and integration pressures are forcing them to move more quickly down the process curve. Once at 28nm, however, they expect to stay there. The advantage of 28nm LP, in contrast to its higher-performance siblings, is that it has few additives other than the germanium and nitrogen sandwiches that stress and strain the silicon so electrons can pass more easily. Neither does LP have high-k metal gates, which add cost to the process compared to more leaky, but cheaper, polysilicon gates. The 28nm process does not have complex 3D transistor structures to deal with. And, although mask-set costs have grown because of the complexities of getting 193nm-wavelength light to draw sub-30nm features, drawing 28nm-process patterns is more straightforward than for the processes that follow it. In contrast to MCU suppliers, the mobile phone chipset suppliers jumped onto 28nm LP and were among the first to ramp up to production volume. Things look to be somewhat different for 14nm and 16nm; processes that require all of the expensive options to work. Companies such as Broadcom – even nVidia – which could make good use of the performance of finFETs, have voiced concerns about the cost of migration and the way it almost turns Moore's Law on its head. In this situation, FD-SOI has a lot going for it. The transistor is better behaved than the same transistor on a bulk silicon process. It is more versatile in that back and forward biasing can deliver huge increases in performance and big cuts in leakage on the same chip, albeit not on the same transistor. There is a very thin layer of insulating oxide underneath the transistor channel. This gives the gates much better control over electron flow in the equally thin channel. FD-SOI does not suffer drain-induced barrier lowering that plagues bulk silicon in nanometre geometries. In a number of ways, a finFET is like an FD-SOI transistor turned on its side. But, because the transistor remains a planar structure, it is far easier to cut a hole in the oxide and wire that up to a voltage source to bias the silicon under the channel in either direction. But the designer doesn't have complete freedom over biasing. The transistor sits in either a p-doped or an n-doped well – which one depends on the biasing strategy. To provide a forward bias and effectively overdrive the transistor, CEA-Leti and ST developed the 'flip well' structure that swaps the normal doping for its opposite. This lets the designer apply a forward bias of up to 3V to give the transistor a massive speed boost, but only -300mV for the reverse bias to cut leakage when the device does not need to switch (see figs 2 and 3). Sticking with the standard layout cuts leakage approximately sixfold through reverse biasing, with just 300mV available for a small performance increase. A port by ST of the ARM Cortex-A57 to 28nm FD-SOI achieved a maximum clock frequency of 3GHz through forward biasing and it could slash power consumption by running at a nominal 0.5V, albeit at 300MHz. Companies such as Qualcomm like the idea of applying these bias voltages. The company's vice president of engineering Geoffrey Yeap cited it as a key advantage in his keynote at IEDM 2013. But such organisations have held back from moving to FD-SOI because of cost, as well as through concern over whether ST has the ecosystem to provide long term manufacturing support. By signing Samsung as a second foundry for 28nm FD-SOI, ST may overcome the supply worries. But because FD-SOI is a speciality process when the mainstream work in foundries has been in finFETs, coupled with the higher cost of the sophisticated wafers needed to support the process, FD-SOI has cost issues of its own. And ST cannot currently offer higher density as its 14nm process has yet to reach production. ST claims its 14nm FD-SOI process should be cheaper than a comparable finFET technology because making the core transistor involves fewer complex steps. Routing between transistors is causing further problems. The 'back end of line' (BEOL) processes used to deposit successive layers of metal onto a die used to be the cheaper half of the process by far. Without the move to the finFET structure, BEOL production would account for 50% of the die cost, up from around 40% at 28nm. And the proportion will increase further with 10nm. Foundries have applied increasingly exotic techniques to the lower metal layers that wire together transistors and cells at the local level. There is hardly any space between the transistors themselves to land contacts, forcing some of the scaling factors up into the metal stack. Since the 32nm node, two local interconnect layers have appeared underneath the first 'true' metal layer. And the second metal layer now has the same pitch as the first; in older processes it was spaced more coarsely. Although foundries have used careful redesign of standard cells to limit the density of wiring needed for the local interconnect, foundries can no longer use standard 193nm lithography to make the masks for these lower, fine-geometry layers; they have to split the design onto two masks, then overlay them very carefully because a shift in registration of more than 3nm spells a disastrous loss of yield. At 10nm, they will either need three masks or to rework designs so they are more regular and probably less space efficient. Then, they can take advantage of chemical techniques to split patterned features into pairs. Both scaled FD-SOI and finFETs will face the same problems with routing. Designs that can use pure performance to justify the cost increase will likely move to 14nm or 16nm finFETs and beyond, but chipmakers will have to think long and hard about the economics of scaling unless there is a breakthrough in the cost of routing or in the front-end processes used to build vertical transistors or speciality wafers. Silicon scaling has never been more complicated and the issues go way beyond the two types of transistor – FD-SOI and finFET – slugging it out at the bottom of the stack.