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ST pursues the wider option when it comes to supply voltage for future transistors

4 mins read

At this year's International Solid State Circuits Conference (ISSCC), STMicroelectronics and research institute CEA-Leti described a DSP with an operating voltage of 400mV, rather than the conventional 1V.

Research has shown for years that trimming the supply voltage can cut power consumption, which has led processor designers, such as ARM and Intel, to investigate whether they can use sub- and near threshold logic (NE, 11 March 2014). In 2002, a group from McMaster University in Canada created a voltage controlled oscillator that ran from an 80mV supply on a 180nm process – a fraction of that process' nominal supply voltage of 1.8V. To cut the supply voltage to such a low level, the McMaster design made extensive use of forward and back biasing to allow it to run from its lowest supply voltage up to 1.8V. ST has revisited the idea of using body biasing to extend the voltage range of processors, not only to give them sudden speed boosts when needed, but to also let them hold state with very little leakage when there is very little to do. Normally, the body of the transistor stays close to 0V, with the voltage on the gate electrode providing the control needed to switch the device on and off. But, as transistor operation depends on the voltage differential between gate and channel, altering the voltage of the silicon body relative to the gate can help the transistor to switch using a lower gate voltage, reducing power consumption for the same performance. If the voltage provides a reverse bias, it can cut leakage; useful for cutting the passive power consumption of temporarily inactive transistors without having to save their state and turn off their supply completely – which takes time. The bad news is the ability to use body voltage control, or biasing, has fallen away with smaller process geometries. Reverse body bias increases the probability of electrons tunnelling through what are now heavily doped layers and leaking away – killing one of the supposed benefits of the technique. Startup SuVolta is trying to address this problem on standard bulk CMOS processes by adding buffer layers underneath an undoped silicon channel and then using body biasing to control performance. Fujitsu launched an image processor last year using the technique and claimed a 30% power reduction, compared to existing products. ST has developed a fully depleted silicon on insulator process (FD-SOI), to boost transistor performance. Transistors built on FD-SOI have a very shallow channel, which improves the gate's ability to remove carriers from that channel when the device needs to be switched off. David Jacquet, CPU architect at STMicroelectronics, claims FD-SOI provides a more convenient way to deploy body bias. "In bulk, you have a link between body bias and supply voltage. But in FD-SOI, you can do what you want." Gerd Teepe, director of design engineering at GlobalFoundries, said at the recent DATE Conference in Dresden: "We need to think of ways to reduce the supply voltage without cutting into performance. If we think about using FD-SOI and finFETs, combined with back and forward bias, then this is a problem we can solve with design." The bad news, says CEA-Leti researcher Fabien Clermidy, is that you can't combine full reverse and forward body bias so that you can ultra low leakage transistors when not switching that kick into high gear when operating using forward body bias. The designer has to make a choice over which to use or else the diode effect that plagues bulk CMOS body biasing crosses over into the FD-SOI world. "One is good for leakage control, the other is used to boost device performance," says Clermidy. On the DSP outlined at ISSCC, designers used body bias voltage scaling from 0V to 2V to increase the achievable clock frequency fourfold at 500mV – where the logic slowing effects of near threshold take a firm grip – and and more than doubling it at 1.3V, compared to non body biased circuitry. Jacquet says forward body bias could be increased to 3V. But leakage is a concern as the forward voltage increases. "When you do forward body bias, you can increase leakage by a factor of six. But you do get more performance with the lower supply voltage, which reduces your initial leakage." The ST design went further than simply turning up the body voltage to make sure critical paths could switch at the desired frequency. 'Canary circuits' on the chip let the processor measure its own performance and cut the operating voltage to the bare minimum – close to 450mV. Clermidy says standard circuit design techniques can be expected to work with voltages as low as 600mV, with low energy signal processors for the Internet of Things and embedded control being prime targets. Although DSPs themselves have taken a back seat in the past decade, relative to general purpose processors, the focus on energy consumption in SoCs is leading the industry back towards heterogenous architectures, in which DSPs and accelerators are coupled with general purpose processors. A project that got the go ahead from the German government at the start of April 2014 will use the FD-SOI process to build a series of heterogenous multiprocessors for automotive systems. Jens Benndorf, managing director of consortium partner Dream Chip, said driver assistance systems will need to deliver high performance at low power. In its contribution to the Things 2Do project, Dream Chip will couple two of Tensilica's general purpose processors with two DSP oriented vector processors. Although body biasing is not yet practical on finFET based processes, ST faces an uphill struggle encouraging other companies to adopt the FD-SOI technology. The company has limited production in its fab at Crolles. "ST can't provide the number of chips required by very big customers," says Clermidy, adding that a deal with GlobalFoundries will provide volume capacity. FinFET processes have an advantage in having the backing of major chipmakers and foundries, together with EDA tools suppliers and IP companies. Jack Harding, president and CEO of eSilicon, says support from the design ecosystem is vital for a technology like FD-SOI to compete with finFETs, which have stronger backing from Intel and the major foundries. "Without the support ecosystem, they will struggle to sell it to anybody." But through projects such as Things 2Do and other European initiatives, CEA-Leti, ST and others are trying to bootstrap a viable design ecosystem. German EDA company MunEDA has been recruited to develop specialised tools to support FD-SOI and to provide a way to migrate IP to FD-SOI. Some IP companies, such as memory specialist Memoir Systems, have already ported some of their IP to the process to aid ST's attempts to build a customer base in network infrastructure equipment. Laurent Remont, ST's vice president of technology and product strategy, says commitment to the process is building. He claims some 20 designs are now underway that will use FD-SOI in some form and that the company is keen to build a wider ecosystem around the process. "We believe strategic alliances are key. We are pushing hard to have a full ecosystem with the possibility of using the process at various foundries. But things have changed a lot in the past three to six months, thanks to customers adopting this." "In terms of cost and performance, it's probably the best technology Europe has ever had," Clermidy concludes.