Stem the tide

1 min read

TSMC’s 45nm process could see the topic of gate leakage spring up, but can the new technology stem the tide? By Mike Richardson.

From September this year, the launch of TSMC’s 45nm process will accelerate the adoption of new technologies. End products are expected to achieve 40% greater functionality or 40% smaller die size, with reduced power consumption, depending on customer requirements. These factors are crucial for SoC designs with ever smaller footprints for mobile phones, portable media players, PDAs and other handheld devices. TSMC’s 45nm process employs a combination of 193nm immersion photolithography and low-k (ELK) material. With a high gate density and a high density 6T sram cell, more than 500million transistors will fit into a 70mm² die area. TSMC’s low power (LP) 45nm process is expected to be available first, followed soon after by the general purpose and high performance (GS) process. “Primarily, the move to 45nm is to satisfy the industry requirements for cost effective solutions,” explained Gareth Jones, director of business operations, Europe, for TSMC. “TSMC recognises that low power is becoming ever more critical and the number of battery powered applications requiring longer lifetimes without having to replace or recharge batteries – particularly in consumer applications – is becoming the dominating feature.”