TSMC launches 40nm process

The node, which is initially available in general purpose (40G) and low power (40LP) variants, enables active power to be reduced by 15% over 45nm whilst more than doubling the gate density achievable with a 65nm process. "Our design flow can take designs started at 45nm and target it toward the advantages of 40nm," said John Wei, TSMC's senior director of advanced technology marketing. "A lot of our development work has gone into ensuring that this transition is truly transparent. Designers need only concentrate on achieving their performance objectives," he said. TSMC has developed the 40LP for leakage sensitive applications, such as wireless and portable devices, whilst the 40G variant is aimed at performance applications, including cpu, networking and fpga designs. Both processes now boast the smallest available sram cell size of 0.242µm2. The process uses a combination of 193nm immersion lithography and extreme low k material. The logic family includes a low power triple gate oxide option to support high performance wireless and portable applications. Meanwhile, there are mixed signal and rf options, as well as embedded dram. According to TSMC, the first wave of 45 and 40nm customers have already used more than 200 blocks on completed multiproject wafer runs. The 40G and LP processes will initially run in TSMCs Fab 12 and will be transferred to Fab 14 as demand ramps.