Packaging pushes performance: How the bandwidth of DDR applications can be extended

The trend is toward higher data rates and lower voltages. For a system to function accurately, its signal integrity performance has to be optimised and must meet certain minimum requirements. Although DDR2 and DDR3 are not as fast as a Serial Link interface, the signal integrity issues are challenging and will be greater for DDR4. This is due to the parallel versus serial nature of these interfaces. Signal integrity concerns, such as crosstalk, jitter, power supply noise and reflections, are dominant for parallel interfaces and get increase with data rate. With the shift toward DDR3 and higher data rates, the period during which data can be sampled reliably (the data valid window) shrinks steadily and sensitivity to signal integrity issues increases dramatically. The package becomes an important consideration at these high data rates, especially with respect to the chip interconnect method. The current IDT DDR3 package is configured to be a wirebond die, but there are benefits in changing to a flip-chip type and the performance benefits are outlined below. DDR interface challenges First generation DDR interfaces were designed for a maximum rate of 400Mtransfer/s, with the respective bit period or unit interval (UI) of 2.5ns. These interfaces typically used a 2.5V power supply. Current DDR3 interfaces run at 1600Mtransfer/s, with DDR4 based systems expected to run at 3200Mtransfer/s. At that rate, each UI is about 312.5ps, with the power supply dropping to 1.2V. Some of the challenges encountered include: • Shrinking bit period. This brings a shorter setup and hold time window, making it harder to meet timing between clock and data signals • Fast signal edges: Shrinking bit periods mean sharper signal edges, exacerbating crosstalk and power supply noise performance • Lower voltages: For a 2.5V supply, a 5% noise tolerance results in a maximum acceptable level of noise of 125mV. For a 1.2V supply, a 5% tolerance translates into 60mV of acceptable noise. Interconnect design and selection therefore becomes critical. Packages are a critical component of the total system interconnect and a sub optimal selection can degrade device performance significantly. Today, IDT's DDR3 devices use wirebonds to connect the chip to the package substrate. The 3d nature of the wirebonds makes controlling the electromagnetic fields emanating from aggressor signals difficult to manage. Wirebonds, in general, are inductive and the mutual inductance between two neighbouring wires is a major contributor of signal to signal crosstalk. Inductive wirebonds also cause the power supply impedance to increase, resulting in more power supply noise at the chip. Converting to a flip-chip package will eliminate a key source of signal integrity concerns without impacting the overall package form factor (see fig 1). Understanding crosstalk Crosstalk is caused by the leakage of electromagnetic signal energy from one conductor to another through mutual capacitance (electric field coupling) and mutual inductance (magnetic field coupling). • Capacitive crosstalk In a victim-aggressor situation, capacitive crosstalk injects current from the aggressor line onto the victim line, with the magnitude of crosstalk proportional to the rate of change of voltage and the amount of mutual capacitance between the two lines. The injected energy will split and flow toward both ends of the victim line – both ends being near end (close to the driver side) and far end (close to the receiver side). • Inductive crosstalk Crosstalk due to mutual inductive coupling induces a voltage on the victim line proportional to the rate of change of current on the driven line and the magnitude of mutual inductance between the two conductors. The current due to the induced voltage flows in the opposite direction of the driven line from the far end to the near end (based on Lenz' law). In substrate based packages, there are two crosstalk components: crosstalk in the transmission line section of the package interconnect; and crosstalk in the 3d structures, such as vias, wirebonds and solder balls. In the transmission line section, crosstalk is predominantly electromagnetic; in the 3d section, it is mostly inductive. For most packaging applications, far end crosstalk is usually negative, identifying inductive crosstalk emanating from the 3d sections of the package as the dominant mechanism. With the wirebonds eliminated (mutual inductance reduced), the flip-chip version of the package shows less far end crosstalk than the wirebond version (see fig 2). Crosstalk effects on modal delays The flight time of a signal through a conductor depends on how neighbouring coupled conductors switch. This difference in flight time gets exacerbated as crosstalk increases. In a multiconductor system, there are three possible switching modes: quiet mode; odd mode; and even mode. • Quiet mode: Where the rise and fall times of the victim signal do not coincide with the neighbouring coupled aggressors or when the victim signal is held quiet. • Odd mode: Where the rise and fall times of neighbouring, coupled aggressors coincide with the victim signal and where the aggressors are switching 180° out of phase with the switching signal. • Even mode: When the neighbouring aggressors switch in the same phase as the victim signal and at the same time. In a coupled system, a signal experiencing odd mode switching arrives at the receiver first, followed by the quiet mode signal and then the even mode signal. This spread in flight time in an I/O bank increases with crosstalk. In a DDR type system, where a common clock samples multiple parallel signal bits, this spread in crosstalk induced skew can have a detrimental impact on the setup and hold time window available for proper clocking. As data rate increases with the associated shrinkage in UI, reducing crosstalk to improve setup hold time windows will become paramount. Fig 3 compares the modal delay spreads of the two packages. Wirebond delay is more spread out, with a total modal delay spread of 41ps, compared to 15ps for the flip-chip variation. With the UI for DDR4 applications expected to be half that of DDR3, this increase in package skew will make timing extremely challenging and flip-chip will be a preferred interconnect option. Power delivery Delivering power to the chip efficiently requires a reduction in the input impedance of the power delivery network looking out from the chip power and ground nodes. Package type and the chip to package substrate interconnect technology are critical components of this network. Package impedance is largely a function of the loop area formed by the power and ground interconnects and the type of chip to package interconnect method used. Eliminating wirebonds from this loop reduces loop inductance – and hence impedance – by more than 50%, with a resultant drop in power supply noise at the chip. Jitesh Shah is a principal engineer with Integrated Device Technology.