Probing questions: How to verify the electrical performance of DDR memory

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Most electronic devices use some form of ram, with sdram dominant in computers and computer based products. Double data rate (DDR) has become the memory technology of choice.

As data transfer speeds increase, analogue signal integrity has become increasingly important for designers, who must guarantee system performance margins or ensure interoperability of memory and memory control devices. Many performance problems, even ones found at the protocol layer, can be traced back to signal integrity issues, so analogue verification of memory devices is a critical step in the validation process. The necessary timing, jitter and electrical signal quality tests are specified by JEDEC, but these can be complex and time consuming; the right tools and techniques can reduce test time and ensure accurate results. One of the first obstacles is acquiring the necessary signals. JEDEC specifies that measurements should be made at the memory's bga ballouts. Since fbgas feature inaccessible solder ball connections, how can this be accomplished? One solution is to include pcb vias beneath the memory components, allowing probing from the back side of the board. Although these test points are not strictly 'at the component ballouts', signal integrity is good and electrical validation can be performed with acceptable test margins. However, maintaining good electrical contact between multiple probe tips and test points can be difficult, so solder down probe connections are usually a better choice. Solder down 'micro coax' probe tips provide a cost effective solution, with excellent signal fidelity and sufficient bandwidth for testing up to DDR3 at 1600Mtransfer/s. Signal access through back side vias may not always be possible: space limitations can prevent the placement of test points and many standard dimms stack memory components back to back to increase density. How can engineers access test points? Fortunately, there are probing solutions. Interposers use a socket that solders onto the target in place of the memory. The interposer, which has test points for probing, then snaps into the socket and the memory component attaches on top. Small isolation resistors embedded within the interposer, as close as possible to the bga pads, are matched to the probe tip electrical network, ensuring signal fidelity. Digital probes also include accessories to access difficult test points. Care should be taken to minimise test equipment impact on the measurements; ferrite cores in the probe tips will reduce reflections on the line. Keeping wire length to the minimum will ensure best signal fidelity. Once signal lines have been probed successfully, the next step is to isolate events of interest. For debug, it may be necessary to isolate events by rank or bank or to isolate specific data patterns for further analysis. Several methods can be used to identify and isolate read and write bursts or other bus conditions. One of the simplest is using the Data Strobe signal (DQS) to identify the start of a read or write burst – DDR3 always asserts DQS high at the start of a write and low at the start of a read. The scope can trigger on this preamble, assuring that only reads or writes are captured at the beginning of the acquired waveform. Advanced Search and Mark (ASM) tools can scan an entire waveform acquisition for a variety of user configurable conditions. One such condition is DDR read/write identification; ASM will find all read bursts or write bursts in an waveform record and mark each burst. In addition, the scope can apply marks as qualifiers for DDR specific measurements, so only the appropriate portion of the data stream is measured. SDRAM commands are synchronised to the rising edge of the memory clock (CK). The four command signals are: chip select (S0# or CS#); row address select (RAS#); column address select (CAS#); and write enable (WE#), where # indicates active low signals. The verification of memory commands requires the scope to probe five command signals – CK, S0#, RAS#, CAS# and WE# – in addition to acquiring the appropriate data (DQ) and DQS signals. The five command signals are then assigned to probe channels in the scope's digital channel menu. Activate Row is the first command in a write or read command sequence. To trigger on the Activate Row command, configure the scope to trigger on a Command group equal to 0011 (S0#=0, RAS#=0, CAS#=1 and WE#=1). Dealing with binary values like 0011 can be error prone, so the scope can work with several data formats. Pattern symbol files are used when a group of signals defines a logical state. JEDEC specifies a number of parameters for each memory technology. One example is measurement reference levels; certain voltage reference levels must be used when making timing measurements. To manage JEDEC specified measurements, it can be valuable to have an application specific measurement utility. Such an approach ensures measurements are configured properly, eliminating the extended setup processes required by general purpose tools. JEDEC measurements can be automated, such as with Option DDRA on Tektronix 70000 scopes. DDRA works with two other software packages: ASM (described above); and the DPOJET Jitter and Eye Diagram Analysis Tools. These three utilities create an easy to use DDR testing and debug suite. The DDRA menu interface has five steps. In step one, the user selects the DDR generation and speed grade. Step 2 allows the particular measurements to be selected. The remaining steps guide the user through probing and offer opportunities for customising or adjusting parameters. Once setup is complete, the scope acquires signals of interest, identifies and marks data bursts and makes the selected measurements. When measuring data bursts, the software automatically generates an eye diagram, with DQ and DQS overlaid to show relative timing. An sdram Write starts with 'Activate', followed by one or more 'Writes'. Activate opens a specific row in a specific bank for writes and reads. Write opens a specific column in the opened row. It would be a protocol error for the Write command to access a bank that has no open rows. After 'Write', the memory expects that, at a defined cycle, the controller hub will write data to it. The row needs to be closed or deactivated with a Precharge command when writing is completed and another row is to be accessed. The simplest DDR2 sdram command protocol sequence is Activate, Write, Precharge. A consecutive write to write sequence is Activate, multiple Writes and Precharge. A write to read sequence is Activate, Write, Read, and Precharge. You can have any order of Writes and Reads on an open row, but it would be a DDR2 dram protocol error if the memory controller hub sent two Write commands in a row without a Deselect between them. The DDR2 dram will respond to the Write command by reading in data that is strobed by the memory controller hub. Because captured waveform data is available behind the measurement results, further options are available. If a measurement fails, it is possible to identify where in the waveform record the failure occurred. Users can then investigate the exact signal details and characteristics at the time of failure. Software tools make it easy to analyse the captured data and to pinpoint regions of interest. For a PDF of the unabridged article, please click on textronix full.pdf below