A clock distribution IC does not generate a clock signal independently; as such, phase noise cannot be measured unless an input is applied. The term most commonly used to quantify the quality of a clock distribution IC is additive phase jitter, or additive phase noise over a specified band.
Less common is a standard methodology to measure additive phase jitter. This methodology requires the design engineer to dig into clock buffer data sheet details. For example, differences in input slew rate, input frequency and input source phase noise can produce a wide variation in stated clock buffer performance.
Phase noise is a frequency domain measurement in which phase jitter over a defined offset bandwidth can be calculated. There are many reasons for using this method – it’s repeatable and easy to measure and allows an engineer to analyse specific offset frequency bands of interest. Time domain measurements eliminate the possibility of analysing over a specific band afterwards – each band of interest requires an additional measurement – and can inherently provide limiting results. Longer test time is required to capture lower frequency performance; a lower bandwidth scope acts as a low pass filter, which means a high bandwidth scope with high sensitivity is required. In other words, oscilloscope jitter provides a total figure, while phase noise paints a better picture of contributing factors.
To characterise the clock buffer’s contribution to phase jitter, the designer must first measure the source and then the source plus buffer. Phase jitter is then calculated by using equation 1. An assumption often made when calculating phase jitter is that the source and buffer noise are not correlated, but rather composed of purely random jitter. Total jitter can be measured using equations 2 and 3.
Equation 1: Jtotal2 = Jsource2 + Jbuffer2
Equation 2: Jbuffer2 = Jtotal2 – Jsource2
Equation 3: Jbuffer = v(Jtotal2 – Jsource2)
Input slew rate
Additive jitter performance depends on the input slew rate. Lower input slew rates often will result in higher additive jitter. A designer must ensure similar slew rates, as stated in the data sheet, will be used to get the expected results in the application. For example, the actual additive phase jitter will fall short of the stated data sheet performance if the input is a clipped sine wave or a sine wave for some temperature-controlled crystal oscillators (TCXOs) or oven-controlled crystal oscillators (OCXOs). In this case, the only option is to measure the clock buffer performance, as the data sheet value will be irrelevant.
It will also be helpful to compare slew rates in the additive jitter measurement used when comparing jitter between various clock buffer manufactures’ data sheets. Figure 1 shows how additive jitter changes over various slew rates. More importantly, it also shows that a buffer may not be superior over all slew rates.
|
Fig 1: A plot of additive phase jitter against input slew rate for two clock buffersInput phase noise
To ensure accurate measurement results, the source phase noise must be significantly lower than the device under test. Often an OCXO is used as a source, but this becomes more difficult or at least costly at higher frequencies and can still have limitations at close-in offsets. Using Equation 3 results in 112fs of additive jitter for the Si53302 clock at 156.250MHz input over frequencies ranging from 12kHz to 20MHz.
However, when using a source with a similar or slightly lower phase noise floor as the buffer, then an overly optimistic additive phase jitter number will be reported.
Therefore, a designer must use caution when comparing additive jitter based on data sheet values. However, it’s best to avoid relying on the additive phase jitter figures. The phase noise plots can be compared, for example, if two buffers under consideration have a similar phase noise floor; in this case, the additive jitter performance should be similar. If one buffer has a better quoted additive phase jitter, then the advantage may result from how the jitter was measured.
Input frequency
Equation 4 shows the relationship between jitter, noise L(f) and frequency.
Equation 4: Tj rms = 10 L(f)/20 /v2pfo
where:
Tj = rms jitter
L(f) = noise power
fo = frequency
As the frequency, fo, is reduced, the phase jitter is increased (providing a constant noise power). Phase jitter is improved by a factor of two for every twofold increase in frequency, if phase noise performance remains constant, which is why most data sheets quote performance at high frequencies. Designers must exercise care to determine the additive jitter performance at the frequency of operation. Additionally, the phase noise performance, L(f), of a buffer can change slightly versus operating frequency. Figure 2 shows the additive jitter performance for a clock buffer versus input frequency, using an adequate low noise source.
|
Fig 2: A plot of additive jitter versus frequency for the Si53302 clock bufferConclusion
Designers must take care when evaluating clock distribution IC performance using data sheet specifications and when designing a buffer in a circuit; differences between input slew rate, input frequency and input source phase noise can produce wide variations in performance.
- Higher slew rates result in lower additive phase jitter.
- Higher frequencies result in lower additive phase jitter.
- Higher input phase noise can result in lower additive phase jitter.It may insightful to compare the stated phase noise performance in addition to the additive phase jitter between various buffers under consideration. For example, does the device with better additive phase jitter also have better phase noise performance? If not, then the measurement technique may be sub-optimal. Theoretical calculations may not apply in all cases. Device evaluation using the intended source may be required to determine the real-world performance and optimal solution.
Author profile:
Fran Boudreau is senior applications engineer, timing products, with Silicon Laboratories.
