The work is focused on stacking up ‘tiles’ or ‘chiplets’ on to one another and, in doing so, packing more computing power into three dimensional chips rather than traditional two-dimension pieces. Intel said that this could allow for ten times as many connections between stacked tiles, meaning that more complex tiles can be stacked on top of one another.
According to Intel this technology will be capable of yielding a 30% to 50% increase in the number of transistors it will be possible to pack into a given area on a chip.
While Intel CEO Pat Gelsinger has laid out commercial plans for the business, this research work shows how Intel plans to compete beyond 2025.
Whether stacking will prove a ‘game-changer’ for the tech giant is open to debate, but one thing is clear Intel has been struggling to compete with the likes of TSMC and Samsung in recent years, as the industry looks to develop smaller and faster chips.
There’s a lot riding on this research.