Engineering publications brought to you by Mark Allen

ASIC & SoC

Integrated prototyping solution to speed SoC development

ST tapes out 20nm test chip using Cadence design tools

Multi fpga partitioning software offers ‘unlimited design capacity’

Quad dsp audio processor to help oem product differentiation

Cadence upgrades verification software

Metasimulator runs 100 times faster than Monte Carlo analyses

Systemic complexity is the chip designer’s biggest enemy

ARM launches quad core hard macro Cortex-A15 MPCore processor

Scalable 32bit dsp cores set to address range of applications

MathWorks enhances range with fpga and asic coding and verification products

Freescale: station on chip delivers industry's highest performance

Broadcom launches world’s first microwave outdoor unit on a chip