These devices include the: TW031V65C, TW054V65C, TW092V65C, and TW123V65C.
An important characteristic of Toshiba’s next-generation process is the consistently low drain-source on-resistance (RDS(ON)) temperature coefficient of the devices. The low RDS(ON) x gate-drain charge (Qgd) figure of merit (FoM) enables engineers to enhance the power density and efficiency of numerous high-voltage applications, including switched-mode power supplies (SMPSs), electric vehicle (EV) charging stations, uninterruptible power supplies (UPS), and photovoltaic (PV) inverters.
The surface-mount DFN8x8 package reduces volume by more than 90% compared to existing lead-inserted packages, such as TO-247 and TO-247-4L(X), improving the power density of equipment while enabling automated assembly.
Surface mounting also reduces parasitic impedance, thereby cutting switching losses and contributing to the low FoM, which improves efficiency.
With less heat needing to be dissipated, high-voltage power system designs can be simpler and more compact, making them suitable for space-constrained applications or furthering miniaturisation.
Furthermore, the multi-pin device allows a Kelvin connection of its signal-source pin for the gate drive. This capability reduces the inductance influence in the source wire within the package, enabling high-speed switching performance. As a result, under specific test conditions, one of the new products, the TW054V65C, reduces turn-on loss by approximately 55% and turn-off loss by approximately 25% compared to existing Toshiba products, thereby helping to reduce power loss in equipment.
