The platform is said to consist of multiple FPGA logic cores designed to make the buffering, formatting and transfer of data between peripherals or sensors and a host PC as straightforward as possible.
With this framework, the company claims the user needs only to create the application specific code to interface to their peripherals and format the data in a suitable manner for transmission to the host PC. This is said to reduce the design effort for common data acquisition and control architectures, thus saving time.
ZestDAQ provides common IP interfaces across multiple boards, which simplifies the porting of designs between Orange Tree’s USB and Ethernet modules. It also includes a host software library and host software examples.
The platform includes a wrapper around the Ethernet interface to simplify network communications and a wrapper around the USB interface to multiplex multiple data streams across a single link. It also provides core code to simplify accessing the control and status registers in a board’s FPGA, and it supports multi-channel FIFO buffering of data in external SDRAM.
