IP cores enable flexible video bridging capabilities

Seven modular IP cores have been added to Lattice Semiconductor's CrossLink FPGA portfolio for increased design flexibility to support consumer, industrial and automotive applications.

According to the company, these modular IP cores offer the building blocks for customers to create their own video bridging solutions.

The IP cores are said to bridge between MIPI and other traditional or legacy display and camera interfaces, allowing customers to support image capture and display applications for delivering augmented and virtual reality, embedded vision and other intelligence at the edge solutions.

The CrossLink modular IP cores include:

  • CSI-2/DSI D-PHY receiver – converts MIPI CSI-2/DSI data streams to parallel data
  • CSI-2/DSI D-PHY transmitter – converts parallel formatted data streams to MIPI CSI-2/DSI
  • FPD-LINK receiver – converts FPD-LINK video streams to pixel clock domain
  • FPD-LINK transmitter – converts Pixel Data Streams to an FPD-LINK video stream
  • SubLVDS image sensor receiver – converts SubLVDS image sensor video stream to pixel clock domain
  • Pixel to byte converter – converts pixel format data to parallel byte format for D-PHY transmitter
  • Byte to pixel converter – converts parallel byte format from a D-PHY receiver into pixel format

In addition, the company has included a 1:2 MIPI DSI display interface bandwidth reducer, which uses select modular IP cores above to bridge an input video stream into two streams or one lower resolution stream.