When one major supplier of compilers and debuggers was asked whether it had plans to support the architecture, its CEO said it would not viable: there were not enough seats outside Nokia in his opinion to support the port.
Fast-forward to the mid-2000s and it was hard to find an embedded tools supplier that did not have plans for Arm support. Although Arm had taken a big risk on switching to the Cortex-M architecture from the ARM7, microcontroller makers embraced it while the Cortex-A cemented its place at the heart of the nascent smartphone market.
Arm did not win that war by being a better RISC architecture than the competition. It won because of a generational shift. Motorola refused for a long time to make its 68K available as a core for SoCs. So SoC makers found an alternative. Though Motorola later had a go at launching an “ARM killer” few outside the radio manufacturer took it seriously.
Today, we are possibly looking at another generational shift. Arm is nowhere near as resistant to its customers’ wishes as Motorola had been two decades ago but a growing base of SoC makers see the RISC-V community as fitting their needs a lot better. Are they moving to a better instruction set architecture (ISA)? It’s possible. The team from UC Berkeley that developed the ISA argue that they have the benefit of experience across the industry of what works with a RISC architecture and what does not. But it’s not the reason you hear from those who use RISC-V. Similar to Nokia when it wanted a core for its own SoCs, the underlying reason is one of freedom, whether perceived or real.
However, the decisions that are leading some customers away from Arm and towards RISC-V – it is hardly a flood at this point – has a lot to do with larger trends in digital and computer architectures. One is the growing use of custom accelerators. These systems use one or more RISC-V processors but not for the core application. Instead they manage the highly specialised accelerator cores that are often deployed in large-scale arrays across an SoC. One of the most visible implementation programmes is at nVidia: the company is using RISC-V processors to replace the Falcon management core in future GPU and neural-network chips. Alibaba unveiled a RISC-V multiprocessor over the summer followed by a much more heavily customised AI accelerator.
An open-source venture
According to RISC-V Foundation CEO Calista Redmond, the group now has 350 members and produced, so far, 44 chips based on the ISA. Many of those members are suppliers to an ecosystem they hope will grow to challenge Arm and expect to use different mechanisms to the current processor giants in order to get there. The clearest difference is that RISC-V is an open-source ISA. The foundation itself does not supply readymade processor cores in the same way that Arm does, though the UC Berkeley team that developed it has created a start-up, SiFive, to sell synthesisable IP cores.
As an open-source venture, users are able to modify the ISA as they wish though the foundation has taken steps to try to prevent balkanisation. Redmond is keen to stress how elements of the ISA get frozen so users can treat them as stable over the long term.
Numerous working groups are defining standard extensions that will themselves be frozen to support tools development. The more adventurous – who are happy to use assembler for critical functions – can define their own instructions that build on top of the core ISA.
After years of resisting the idea, Arm is also joining in with the custom-instruction trend. People at the company stress the move is not a reaction to RISC-V but the company announced at Arm TechCon earlier in October that it will now let customers develop custom instructions for cores based on the V8-M. The approach taken by Arm is more restrictive – there are just 16 opcode slots reserved for customised instructions – but it is an indication of how old assumptions of the importance of the ISA are breaking down.
Custom instruction usage is not new to SoC design. Other architectures such as ARC, MIPS and Tensilica support custom instructions. But as performance-per-joule gets greater attention, it is a potentially useful addition in an environment where application-specific accelerators do more of the heavy lifting than general-purpose processors.
The RISC-V Foundation and a number of its members are going further in the belief that there is pent-up demand from electronics manufacturers who would, given the choice, build their own SoCs if it were easier and cheaper. The foundation is backing the Chips Alliance, a group that aims to provide open-source IP around RISC-V and even some EDA tools. The deliverables available today include the SweRV core developed by Western Digital for its storage controllers and the FuseSoC package manager, which can be used to assemble the IP into chip designs.
Impetus for open-source IP that is effectively separated from the original creator has also come from the geopolitical situation. The US-China trade war and the decision by the US to block some Chinese companies from accessing technology has fostered the sense among non-Western organisations that they should seek to reduce their reliance on suppliers who may be forbidden from dealing with them. Open-source IP provides a mechanism for achieving that. At the same time, the RISC-V Foundation has decided to move out of the US and to the Switzerland, which benefit from its perception of neutrality.
Although the RISC-V movement has achieved significant momentum that may be enough to signal a long-term shift in what constitutes the dominant ISA over the coming decade, there are trends that may provide incumbents such as Arm with the ability to maintain strongholds largely because they are almost entirely orthogonal to the choice of ISA. Since clock speeds topped out around 15 years ago, forcing the trend to parallel processing and custom acceleration, the importance of the ISA itself has diminished. More important developments may lie in the interconnects that let the processors talk to each other. Software developers continue to find multithreaded code challenging to write and there are obvious structural inefficiencies in the way most interprocessor protocols work today. Most of the alternatives remain R&D projects and though RISC-V’s nature may make it easier for multiple groups to innovate and drive this forward, a better option may from leftfield and be independent of the ISA.
The choices offered by RISC-V may themselves prove to be too much for most users. Custom instructions arguably should come with a health warning as users run the risk of developing extensions that are only advantageous for a single generation of products but which need to be supported long-term because of legacy software concerns.
These considerations may pale into insignificance when you consider the overall cost of SoC design itself. The boom in Chinese-developed silicon has been propelled by a free-flowing source of investment cash that may not continue into the future as the market winnows out the weaker offerings. For most companies, does the cost of custom silicon justify the market advantage they could obtain. As system-in-package options become cheaper and more effective, many may choose to adopt standard parts and simply augment them with FPGAs or small-scale ASICs – although those smaller devices could easily justify a simple RISC-V implementation or one of Arm’s low-end offerings, which are now sold under cheaper access programmes than the company’s traditional IP licences. A sea-change may be coming to the world of embedded microprocessors but it is not necessarily one where there is an obvious winner.
Chris Edwards is a freelance journalist and contributing editor to New Electronics