Mike Thompson, senior product marketing manager for ARC processors, said: “The superscalar architecture increases performance by about 25%, compared to the previous HS3x family, and doubles the DSP performance.”
The HS46, 47 and 48 have separate 64kbyte instruction and data caches, with the HS48 adding an L2 cache and an MMU. “Power consumption is important,” Thompson added, “because budgets are either fixed or dropping, so we’ve focused on performance and efficiency.” According to Synopsys, the cores consume as little as 37µW/MHz in a typical 16nm FinFET process.
The ARC HS44, HS46 and HS48 processors feature the ARCv2 instruction-set architecture. HS4x cores features a high speed, 10 stage, dual-issue pipeline that supports out of order execution. Typically, the core requires 0.06mm2 of silicon in a 16nm FinFET process. Branch prediction and a late-stage ALU improve instruction processing efficiency.
The HS45D and HS47D offer additional DSP capabilities, allowing designers to implement a hardware integer divider, instructions for 64bit multiply, MAC, vector addition and vector subtraction. A configurable IEEE754 compliant floating point unit offering single or double precision is also available.
