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SRAM IP demonstrator chip cuts power consumption in half

UK start up sureCore has taped out its low power sram IP demonstrator chip in STMicroelectronics' 28nm Fully Depleted Silicon-on-Insulator (FDSOI) process.

The device is designed to significantly lower active power consumption. sureCore says it delivers greater than 50% power savings compared to current offerings in the same process. In tests, the sram IP memory demonstrated 75% less power for read cycles and 50% for write cycles. In addition, the technology promises improved leakage performance, saving between 20 and 40%. Paul Wells, sureCore ceo, said: "This is a major milestone for the company - the demonstrator device will allow us to take the next steps commercially. "Although it is implemented in an FDSOI process, the innovations developed by sureCore are not process specific and will map to both bulk cmos and FinFET technologies. We are currently working closely with partners to implement this in 40 and 28nm bulk cmos."