The collaboration will be targeting one of the industry’s key performance challenges, that is to optimise the use of DRAM and emerging memories to create a high-capacity memory subsystem that delivers comparable performance to DRAM alone.
As part of the collaboration, Rambus Labs and IBM will develop a flexible prototype hybrid memory platform using the OpenCAPI interface to demonstrate performance of multiple memory types in real-world server applications.
“The exploding volume of data and rapidly evolving workloads for Big Data applications are placing tremendous pressure on data centre memory systems for increased performance and capacity,” explained Laura Stark, senior vice president and general manager of the Emerging Solutions Division at Rambus. “This project demonstrates our ongoing collaboration with the industry to accelerate the development and adoption of advanced memory solutions.”
Rambus will leverage IBM’s POWER9 processor and its OpenCAPI high performance interface to build a Hybrid Memory and development subsystem prototype. To move forward on this project, Rambus is also joining the OpenCAPI Consortium, an open development community based on Coherent Accelerator Processor Interface technology, and the OpenPOWER Foundation, an open development community based on the IBM Power Architecture.
Commenting Steve Fields, IBM fellow and chief engineer of Power Systems said, “This project leverages the new architecture to combine the best attributes of multiple types of media to achieve new levels of system cost/performance for memory-intensive cloud deployments and AI applications.”
Having high-capacity and high-density memory near the processor will help to improve the overall system performance and increase the ability to more fully use CPU resources.
Rambus and IBM’s hybrid memory system architectures will combine standard DRAM using other technologies such as Flash, enhanced Flash, Phase Change Memory (PCM), Resistive RAM (ReRAM) and Spin Torque Transfer Magnetic RAM (STT-MRAM) to create high capacity memories at lower cost per bit, with performance levels comparable to that of DRAM.