MIPS64 architecture powers Cavium’s new multicore processors

According to Cavium, the processors are designed for the enterprise, data centre, access and service provider markets, which require increasing support for converged data, voice and video. In a bid to address this, the Octeon III is integrated with 1 to 48 MIPS64 cores at up to 2.5GHz, providing up to 120GHz of 64bit compute power per chip. Building on its previous generation Octeon II processor family, the new range incorporates more cores and features to address markets including cloud computing, high end core and edge routers, metro Ethernet, enterprise switches and 3G/4G/LTE basestations. "Leveraging the industry standard MIPS64 architecture and its broad ecosystem built over more than 20 years, we are delivering groundbreaking processors with an unprecedented level of compute power using a standard ISA," said Rajiv Khemani, chief operating officer, Cavium. "We surpassed the world's highest CoreMark Benchmark Score for standards based processors with our Octeon II family in 2011 and we continue to deliver leading edge performance with the release of our Octeon III processors. These processors are proliferating across tier one companies who recognise the unique value of our processors in this new era of terabit computing." Sandeep Vij, president and CEO, MIPS Technologies, added: "Cavium is keeping one step ahead of the industry's appetite for ever more sophisticated multicore processor technologies capable of processing increasingly large amounts of data. We are pleased that Cavium continues its innovation around the 64bit MIPS architecture, which has been the basis of a wide range of networking equipment, servers and other equipment since 1991. As data traffic increases across wired and mobile networks for streaming media, cloud computing and storage networking, companies are increasingly looking to the MIPS architecture to provide the high performance and efficiency needed for the next generation of products." The new range enables multiple chips to be combined into a single logical high performance processor using Cavium's new chip interconnect architecture. All processors incorporate new dedicated hardware engines to speed search, protocol parsing and traffic management, as well as enhanced cryptography, compression and deep packet inspection engines.