Mentor and Cadence announce fan-out WLCSP solutions

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Mentor Graphics and Cadence Design Systems have both released design solutions for integrated fan-out (InFO) Wafer-Level Chip Scale Packaging (WLCSP) technology.

Mentor’s solution comprises the Calibre nmDRC physical verification product, the Calibre RVE results viewing platform, and the Xpedition Package Integrator flow. It is said to enable designers to deploy fan-out layer structures and interconnects in the TSMC InFO technology, for cost-sensitive applications such as mobile and consumer products.

“Integrating Calibre nmDRC technology with the Xpedition Package Integrator flow is a solid first step in Mentor’s support of TSMC’s InFO technology,” stated Joe Sawicki, vice president and general manager of Mentor Graphics Design to Silicon Division. “We continue to work with TSMC and its ecosystem to expand beyond this initial step by establishing a roadmap for additional capabilities to further accelerate time-to-market for users of TSMC’s InFO offering.”

Cadence’s offers what it claims is the industry’s only foundry-proven IC packaging design and analysis solution for advanced Fan-Out WLCSP and 2.5D interposer-based designs. It includes the Cadence OrbitIOTM Interconnect Designer, Cadence System-in-Package Layout and Cadence Physical Verification System. It is said to enable faster multi-chip integration for smaller, lighter and power-optimised wireless mobile devices.

Steve Durrill, senior product engineering group director for the PCB Group at Cadence, said: “Our latest release enables broad WLCSP-enabled design and foundry and OSAT manufacturing signoff, which in turn helps fabless semiconductor and systems companies deliver ultra-thin mobile-focused devices using the latest foundry and OSAT IC package manufacturing approaches.”