Lattice ‘redefines’ mid range fpga offerings, target comms apps

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In a move which it says redefines the low cost, low power mid range fpga market, Lattice Semiconductor has launched the LatticeECP4 family. The range is said to build on the ECP3 family, bringing advanced features to the mainstream while maintaining low power consumption.
"The family offers an unprecedented combination of the premium features, high performance, low cost and low power that is necessary for sophisticated, but cost sensitive, wireless, wireline, video and computing applications," said Sean Riley, general manager of Lattice's Business Group.

The fpgas are up to 50% faster than previous Lattice devices and feature 1066Mbit/s DDR3 memory interfaces and 1.25Gbit/s LVDS I/Os that can be set up as serial Gigabit Ethernet interfaces The ECP4 family features six devices, each offering 6Gbit serdes features, and cascadable dsp blocks. DSP blocks support 36x36 MACs at more than 500MHz, with dsp slices allowing cascadability for wide ALU and adder tree functions. According to Lattice, each dsp block offers four times the bandwidth than its previous devices. Logic density varies from 30k to 250k LUTs with up to 512 user I/O available. Also featured are hardened communication engine blocks, featuring multiple 10Gbit Ethernet and Triple Speed MAC blocks, as well as PCI Express 2.1 and SRIO 2.1 blocks. The 30, 50, 95 and 130 LUT devices can be supplied as wire bonded parts in three fine pitch bga packages, with 484, 648 and 868 pins. All six models in the range can be supplied in a choice of three flip chip bga packages, with 676, 900 and 1152 pins.