The version includes expanded support for the latest Lattice devices based on the Lattice Nexus FPGA development platform and a newly integrated ModelSim OEM simulator from Mentor which extends simulation capabilities to Linux environments. Lattice Radiant design software is intended to accelerate the development of Lattice FPGA-based applications for a range of markets, including industrial/automotive, communications/compute, and consumer.
“As Lattice engages with our customers in defining next-generation features, we continue to invest in ease-of-use and providing new capabilities in our design tools as application needs evolve,” said Roger Do, Senior Product Line Manager, Lattice Semiconductor. “By integrating ModelSim with Radiant 2.2, developers have full access to simulation and other tools to develop more complex FPGA designs on larger capacity Linux workstations.”
Key features of Radiant 2.2 include:
- Simulation tool – Mentor ModelSim is an OEM simulation tool that integrates with the Radiant software tool flow. ModelSim adds support for Linux-based FPGA development and improves overall simulation performance for faster design verification.
- Expanded device support – Radiant 2.2 adds full programming and on-chip debug support for the Lattice CrossLink-NX FPGA for video connectivity and the general-purpose Lattice Certus-NX FPGA.
- Device security – Radiant 2.2 supports full bitstream encryption and authentication to help secure CrossLink-NX and Certus-NX FPGAs against unauthorised access.
- Reveal Analyzer/Controller – real time on-chip debugging support enabled for CrossLink-NX and Certus-NX device families.
“Integrated with Lattice Radiant development software, Mentor’s OEM-edition simulator brings trusted verification capabilities to their users while helping reduce support and software maintenance efforts,” said Moses Satyasekaran, Product Manager, ICVS for Mentor. “With wide-scale adoption across the global semiconductor industry, Mentor’s ModelSim and Questa tools help speed start-up and minimise learning efforts for FPGA teams.”