Intel joins forces with Glasgow Uni as part of European taskforce

The European Commission has established a European taskforce has been created to address the issue of the reliability of microchips as transistors get smaller. The 'Terascale Reliability Adaptive Memory Systems' (TRAMS) consortium includes both Intel and Glasgow University, as well as a number of European organisations. Prof Asen Asenov (pictured), of the Department of Electronic and Electrical Engineering is heading Glasgow University's involvement and believes that terascale computing will transform the power, performance and functionality of consumer devices. He said: "If we are to continue to shrink the size of transistors in order to develop such powerful circuits, we need fundamentally new approaches to circuit and system design that can take account of the variability within transistors. We hope this project will result in new chip design paradigms for building reliable memory systems out of unreliable nanoscale components cheaply and effectively, heralding the era of terascale computing." Simulation software developed by Prof Asenov will be central to the TRAMS project, with all device design and simulation work being conducted at Glasgow. According to Prof Asenov, the 'NanoCMOS simulations' use grid computing, which utilises the processor power of thousands of linked computers, to simulate how hundreds of thousands of transistors, each with their own individual characterstics, will function within a circuit. The TRAMS consortium will focus on future generation of cmos microchip technologies and also consider 'Beyond cmos' technologies; nanowire transistors, quantum devices, carbon nanotubes and molecular electronics, which are expected to be as small as five nanometres. The project is expected to last three years.