IBM dram test chip brings ‘three generation’ leap
IBM has built a prototype dram on its 32nm silicon on insulator (SoI) process. The device is said to bring improved speed, power savings and greater reliability.
According to the company, the embedded dram test chip has the smallest memory cell yet, and improves upon the density, speed and capacity of 22 and 32nm sram. It claims the performance is 'what would be expected of an sram produced in 15nm technology'. A 15nm process is three generations ahead of current volume processes.
Gary Patton, vice president for IBM's Semiconductor Research and Development Center, noted: "Industry leading dense embedded memory and our design library agreement with ARM underscore our ability to provide clients with a market edge and a clear progression path to 32nm and 22nm SOI technology nodes."
IBM intends to offer 32nm SoI technology to its asic and foundry clients and will use the technology in chips for its servers.
