GaN-on-silicon for scalable transistors

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A team of researchers at the University of Illinois claims to have advanced gallium nitride (GaN)-on-silicon transistor technology by optimising the composition of the device’s semiconductor layers. Working with Veeco and IBM, the team developed the high electron mobility transistor (HEMT) structure on a 200mm silicon substrate with a scalable process.

The researchers created the GaN HEMT structure on a silicon platform because it is compatible with existing CMOS manufacturing processes and is less expensive than other substrate options like sapphire and silicon carbide.

"When you grow the GaN on top, there's a lot of strain between the layers, so we grew buffer layers to help change the lattice constant into the proper size," explained ECE undergraduate researcher Josh Perozek.

Without these buffer layers, cracks or other defects form in the GaN material, which prevent the transistor from operating properly. Specifically, these defects are said to ruin the properties of the 2D electron gas channel, critical to the HEMT’s ability to conduct current and function at high frequencies.

After studying three different buffer layer configurations, the team discovered that thicker buffer layers made of graded AlGaN reduce threading dislocation, and stacking those layers reduces stress. With this type of configuration, the team achieved an electron mobility of 1800cm2/V.s. Typical electron mobility for silicon at room temperature is 1400cm2/V.s.

"The less strain there is on the GaN layer, the higher the mobility will be, which ultimately corresponds to higher transistor operating frequencies," concluded Hsuan-Ping Lee, graduate student researcher.