Forget design for reuse; the new mantra is ‘build for change’

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In his keynote speech at last month's IPSoC conference – held in Grenoble's World Trade Centre – Cadence senior vp Martin Lund announced that IP reuse is an illusion. "The standard IP 'mall' concept is no longer working," he said. "Today, we need a factory approach to IP."

Third party IP vendors have, for years, said that assembling proven, reusable IP building blocks is the best way of creating complex devices within tight timescales. But now, it seems, design reuse is no longer the solution, if indeed, it ever was. Even the most basic standards based IP building blocks featuring in third party IP catalogues are developed to suit different protocols, interface standards or process nodes. In addition, many have a number of parameters that need to be specified more precisely, resulting in many potential configurations. When it comes to the next project, Lund maintains, some element will have changed such that the IP block is either no longer suitable, or requires some modification. He accepts that an IP block may still (but not always) be reused to generate derivative products as part of a platform based design approach. "The factory approach is better, where we can offer customers customised IP, tailored to their specific requirements, yet retaining the quality, reliability and support they expect from a third party IP vendor," Lund explained. This shift in emphasis to delivering customised IP is aimed at overcoming systems houses' reticence to procure third party IP precisely because it cannot (normally) be configured or tweaked exactly how they would like. "The aim is to design IP that can be modified and configured within a set of parameters, rather than hacking a finished design," Lund continued. The use of advanced verification technologies combined with the vendor's extensive expertise will assure the quality levels demanded by customers, he added. The Cadence IP factory concept is being applied to its range of DDR memory controller IP and will expand to embrace its semiconductor IP catalogue. Design reuse champion and arch rival Synopsys agrees the IP business is changing. Joachim Kunkel, senior vp of its Solutions Group, commented: "Design reuse is not happening as it was. No two customers take the same configuration and one customer never takes the same configuration twice," he confirmed. However, Kunkel disagrees that design reuse is dead. From the IP developer's perspective, a large part of a design, probably more than 90%, is common to all variations. "And, typically, the verification environment is reusable," he added. An exception is moving to a new process node, which generally requires considerable redesign. Synopsys claims it has long offered highly configurable (by the vendor) IP, although this is not always fully appreciated by customers, Kunkel admitted. Lund concurred, commenting that IP trading, at times, is like haggling in a bazaar. Meanwhile, Gabriele Saucier, ceo of IPSoC organiser Design & Reuse, said the term 'reuse' refers to the know how, not the block itself. "IP blocks are never reused in exactly the same configuration," she said. "It has always been so." Lund, who is new to his job and to the vendor side of the IP/SoC sector, is clearly taking a fresh approach. One industry watcher in Grenoble commented that, with Lund as head of Cadence' s SoC Realisation Group, and having spent 12 years with IP developer and user Broadcom, Cadence may be about to challenge Synopsys' dominance of the IP market. Other IPSoC news Node skipping Synopsys' Joachim Kunkel's keynote focused on the impending move to 20nm and the impact it will have on analogue/mixed signal IP. Synopsys has been tracking closely how long it takes the industry to transition from one node to the next. While the shift from 90nm to 65nm to 45nm to 28nm has taken much the same time, Kunkel said he is noticing distinct changes in the pattern as customers begin to look at 20nm. Analysis of the design rules, power vs area considerations and reliability simulations all indicate that a change of architecture for analogue and mixed signal designs has become necessary. Synopsys has found that designing for 20nm is requiring close consideration of the many process and layout dependent effects. In particular, designers must make extensive density checks. Density fills will be needed, so that circuits that require to be matched, such as memory, are located in areas with the same density. "We are seeing some customer resistance to moving to the next node," Kunkel remarked. Many analogue designers have been resisting the move from 45nm to 28nm, while some who have moved are having 'a nightmare', he added. IP Management tool Design & Reuse, the Grenoble based IP catalogue company, has launched the latest version of its IP Enterprise Management Platform. The latest enhancements enable it to be used as a unified IP data centre with built in intelligent automation. The tool can be tailored for use by IP developers, vendors and users, with customisable dashboards and bridges linking to other in house and external resources. The tool can be used for IP design management for version control and workflow tracking, by IP vendors to track exactly which configurations are delivered to which customers, and by systems houses to track the procurement and licence usage of third party IP blocks. Interface IP winners and losers Eric Esteve of IPnest predicts that use of PCI Express will extend to storage and mobile applications, resulting in 50% growth in demand to 2016. MIPI, already strong in smartphones, will extend to other power conscious mobile applications. Also on the up are: DDR memory controllers, which will see increased interest in third party dedicated hard IP instead of soft phys; network on chip IP; and PHY IP. Meanwhile, Esteve says interest is declining in USB3.0, SATA, x86 cores and Thunderbolt.