A leader in customisable RISC-V processor IP, Codasip has invested heavily into processor verification to deliver high quality RISC-V processors.
Codasip has included Imperas golden reference models in its DV testbenches to ensure an efficient verification flow that accommodates a wide range of flexible features and options while scaling across the entire roadmap of future cores to enable rigorous confirmation of functional quality.
RISC-V is a modular architecture that offer multiple permutations of base instructions, standard optional extensions and custom instructions - that raises concerns about implementations and the risk of fragmentation.
Codasip’s internal testing already uses an internal instruction-accurate model, several sources of direct and random testing (internal and externally provided), and several different technologies to check and ensure processor compliance. Imperas configurable reference models are already fully tested and enable all the configuration options needed to support this comprehensive view.
The Codasip engineering team based in Sophia-Antipolis, France, reviewed the challenges of the evolving RISC-V specifications, the full Codasip processor IP portfolio, extensions and configurable features, plus future roadmap plans and found that the Imperas solutions were able to support the operational workload and scale requirements.
The Codasip engineering team set-up the infrastructure and test frameworks around the Imperas RISC-V Reference Models to efficiently test all configurations with the ability to adapt for new roadmap features.
“Imperas are the pioneers in simulation technology and processor verification for RISC-V,” said Philippe Luc, Verification Director Codasip. “While processor verification is not a new problem, there are many RISC-V suppliers, with customisation and various levels of verification or conformance: customers are legitimately concerned about both quality and fragmentation.
"Codasip is very proud of our rigorous approach to verification and using Imperas as an important part of our quality process furthers extend our differentiation. The Imperas independence, reputation and technical strength provides our customers with further reassurance in our ‘best in class’ RISC-V processors,”
Simon Davidmann, CEO at Imperas added, “Design verification of this processor IP is fundamental to Codasip continuing to deliver the highest-quality processors as it moves to the next generation of its IP. Each additional optional feature roughly doubles the verification workload. The Imperas approach supports Codasip’s development by applying Continuous Integration/Continuous Development to a sophisticated processor DV environment by using simulation and offers an efficiency advantage without compromising optional features.”