ASPEED and CEVA collaborate to improve voice on Cupola360 SoCs

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CEVA and ASPEED Technology have announced that ASPEED has licensed and deployed the CEVA-BX1 audio/voice DSP in its 2nd generation Cupola360 SoC, AST1230 for smart cameras and video conferencing systems.

The companies are also collaborating to address the most challenging conferencing use cases with the availability of CEVA’s ClearVox multi-microphone noise reduction and acoustic echo cancellation audio front end (AFE) software. This software package has been fully optimised for the CEVA-BX1 DSP, enhancing the intelligibility of any voice conferencing system and allowing voice assistants and hands-free control capabilities to be added.

Chris Lin, Chairman and President of ASPEED Technology, commented: “Our 2nd generation Cupola360 SoC is our first product to incorporate real-time multi-image stitching video and powerful audio processing capabilities, making it perfect for video conferencing applications.”

The company's 2nd generation Cupola360 multi-image stitching video & audio SoC, AST1230, as well as the accompanying app, is specifically designed for high performance video conferencing applications. With a focus on advanced smart cameras for spherical video conferencing applications, the AST1230 SoC features include a powerful image signal processor (ISP) and a smart layout processing engine.

Incorporating ASPEED’s Hyper-stitching technology, the AST1230 SoC is engineered to deliver extraordinary processing power for on-device real-time image stitching. Incorporating the high level programmable CEVA-BX1 DSP to tackle challenging audio/voice use cases, the AST1230 SoC offers a combination of power and thermal efficiency, making it suitable for a wide range of emerging IoT applications.

Additional features include 8 digital MIC inputs with powerful audio processing algorithms, including far-field speech, beam-forming, auto gain control (AGC), noise suppression, and echo cancelation.

The CEVA-BX1 processor combines efficient DSP compute capability with high-level programming and compact code size requirements of embedded applications.

Using an 11-stage pipeline and 4-way VLIW micro-architecture, it offers parallel processing with a Single Instruction Multiple Data (SIMD) ISA, widely used in neural networks inference, noise reduction and echo cancellation, as well as high accuracy sensor fusion algorithms.

The CEVA-BX1 is also accompanied by a software development tool chain, including an advanced LLVM compiler, Eclipse based debugger, DSP and neural network compute libraries, neural network frameworks support in the form of Tensorflow Lite Micro, and choice of industry leading Real Time Operating Systems (RTOS).