The project, developed for a 5G network infrastructure vendor, combines technology from the two companies to deliver a solution that increases reliability while reducing latency and power consumption for the most critical components of the 5G physical layer.
The design provides a low-risk, fast time-to-market solution for 5G equipment vendors to drive the O-RAN industry forward. For the design, AccelerComm’s PUSCH Decoder and the PDSCH Encoder were integrated onto the Intel Stratix 10 DX FPGA, which is a part of Silicom’s N5010 card utilizing Intel Open FPGA Stack (Intel OFS) Software infrastructure, to provide a Layer 1 High PHY accelerator function.
The O-RAN Alliance is transforming the approach taken by the mobile industry is designing and deploying Radio Access Networks (RAN), and is moving it towards a more open, intelligent, and fully interoperable approach from multiple vendors. This enables vendors such as AccelerComm and Silicom to partner and bring their expertise to market, replacing the closed ecosystems which typically involve just a single vendor.
“For 5G to meet its full potential it is critical that the whole O-RAN ecosystem works together to maximize the benefits from this technology,” explained Rob Barnes, Chief Commercial Officer at AccelerComm. “Working with Silicom we are combining our areas of expertise to produce a solution which significantly improves spectral efficiency and network performance while reducing resource requirements and power consumption for 5G RAN equipment, helping deliver on the promise of Open RAN.”
“When we developed the N5010 Stratix 10 based platform, we had in mind 5G/O-RAN performance boosting, which is what AccelerComm has achieved through their implementation on our platform. This project demonstrates the power of collaboration within the Open RAN community,” added Nadav Yafe, VP Business Development and Product at Silicom.