The work of Robert Noyce, who later went on to co-found Intel, was filed at the end of July 1959 and became the one that most industry watchers remember.
But Future Horizons’ president and CEO Malcolm Penn likes to point out that Jean Hoerni’s work, filed two months earlier, provided the framework for Fairchild’s semiconductor business to take off and the rest of the industry with it.
It described the planar process that, despite many changes, continues to drive the technology forward. But the relentless progress in linear scaling that began as Hoerni’s and Noyce’s ideas were put into action is now gradually getting bogged down in the mud.
There is some disagreement as to how bogged down the industry has become. Tom Beckley, senior vice president of the custom IC and PCB group at Cadence Design Systems, says: “Physics challenges will overwhelm the world of chip design.”
The question is how soon those challenges become critical. Joe Sawicki, executive vice president of Siemens’ electronic-design subsidiary Mentor is confident there is still room for further scaling, at least up to 2025.
At the Semicon West show earlier this month, Synopsys chairman and co-CEO Aart de Geus pushed his estimate out to a full decade, but noted: “Maybe it’s not exactly the same kind of curve that Moore actually drew. That doesn’t matter.” What is important, he argued is that the exponential increase in density can increase in some way.
Novel ideas such as double-decker transistors developed by imec for the 3nm node, due in four or five years, could help keep the promise of a doubling in density per square millimetre alive even as it becomes more difficult to reduce the physical distances between transistors on a 2D floorplan. But the costs of development for those still in the game of planar scaling continue to grow.
Last summer, foundry GlobalFoundries decided it could no longer fund the development of its own 7nm process and threw in the towel, choosing instead to focus on the silicon-on-insulator (SOI) processes that started life at STMicroelectronics and CEA-Leti in Grenoble, France. It has been far from smooth for the bigger guns of the industry. Intel has struggled to move its 10nm process into production while both Samsung and TSMC are readying their 7nm processes. However, despite the naming they have similar physical attributes to Intel’s 10nm. The adoption of extreme ultraviolet (EUV) lithography should improve the chipmakers’ ability to continue scaling. But even the likes of Intel see even the drive for full monolithic integration falling off.
New opportunities
At the company’s late spring investor meeting, Intel chief engineering officer Venkata Murthy Renduchintala said: “Going forward, Intel is expanding the formula of integration well beyond the single die. This approach allows us to prioritise R&D in areas where performance is most correlated with logic scaling. And in other areas where it’s not, we have the option of selective outsourcing and thereby focusing our capital investments where we’re most differentiated.”
Intel’s Foveros expands on the system-in-package (SIP) work the company did with its silicon interposer technology currently used in the Programmable System Group’s FPGAs. Whereas the Embedded Multi-die Interconnect Bridge (EMIB) is used to connect chiplets inside a package that are mounted side by side, Foveros uses an approach similar to that employed by the memory stacks such as HBM proposed for high-end compute accelerators and adopted by Xilinx for its new generation of FPGAs. In these designs, through-silicon vias (TSVs) provide the connection between individual chips that are stacked on top of each other.
“This project started in 2016 with one of our largest customers. And the goal was to architect the future of intelligent agents. Together, we defined some pretty ambitious and challenging goals. As we translated these goals into platform technical specifications, we found ourselves with a technical conundrum. We needed a 12 x 12mm form factor. That meant we couldn’t use 2D or planar design,” Renduchintala explains. Long-term battery autonomy called for low-leakage transistor technology certain parts of the IP into one device. “At the same time, we needed uncompromising performance from our compute engines. And this meant we needed access to 10nm technology.”
The open question for TSV-based integration remains one of cost. Steve Mensor, vice president of FPGA maker Achronix, says the company decided against combining its upcoming Speedster 7t devices with HBM memory. Achronix opted to use a GDDR6 interface to off chip memories instead of the stacked-memory HBM. “There are debates in the industry and even within Achronix over this. HBM is uncontested in terms of form factor. The debate comes in when you talk about pricing. HBM is extremely expensive today, though there are roadmaps to improving that.”
Because it restricts the TSVs to one layer and puts them into chips made on older and cheaper processes, the cost adder for an approach such as Foveros is less than with full HBM stacks. But it points to limited scaling of 3D integration later on. However, it is a different story for memories and Gurtej Sandhu, senior fellow and vice president at Micron Technology, pointed out at the Design Automation Conference (DAC) that in terms of devices made, memory accounts for 90 per cent of the market. Focusing much of the attention on memory scaling could do much to keep the overall industry on track for its expected exponentials.
Gurtej Sandhu, says changes to DRAM architecture, the shift to 3D flash mean “there is no planar in memory anymore; it’s all 3D. The capacitor in DRAM went into 3D in the mid-1990s and the transistor in the 2000s. This is not to sound as though I’m crowing about it but with 3D as well as new materials, memory was using this approach five to ten years before logic”.
Penn says the commercial arrival of 3D NAND represented something like ”a Jean Hoerni moment”, with an approach that completely rethinks production methods by turning formerly flat structures 90° and forming them vertically.
Because the manufacturing methods for these 3D memories rely more on precision etching and deposition than lithography, which is the main issue in logic, bulk-memory processes could lead to a restart of work on wafer-size increases beyond 300mm to gain further cost benefits.
Companies such as Micron expect to see much more cooperation between logic and memory manufacturers in tandem with the rise of 3D integration. Sandhu sees applications such as machine learning providing the impetus for memories that are heavily customised rather than expecting customers to continue to buy more general-purpose devices.
As well as cost design for manufacturing and reliability issues remain for 3D integration.
Vic Kulkarni, vice president and chief strategist at Ansys, says teams need to analyse how their proposed products will behave under mechanical stress and temperature changes.
“You have to look at what happens to solder joints around the package and the effects of thermal warpage,” he says, although the development of glass interposers can help reduce the problem through the use of additives to match expansion coefficients.
At Semicon West, Applied Materials CEO Gary Dickerson attempted to sum up the mood: “There’s no question that classic 2D scaling has run out of gas but there are all of these new opportunities for innovation in materials, architectures and packages.”
