The benefits of using 600V GaN cascode fets

More recently, the focus has been on development of cost effective, high performance GaN based devices for power electronic applications. The fundamental GaN building block is a high electron mobility transistor (HEMT) made of various GaN layers grown on a substrate. Silicon is the preferred substrate because it is readily available in large diameter wafers at low cost. Alternative substrates, like SiC or sapphire, might make it easier to grow the GaN layers, but their prohibitive cost makes it impractical to commercialise and enable wide adoption. The HEMT is fundamentally a fast, normally on device that can be turned off by applying a negative gate bias voltage. The depletion mode (normally on) characteristic can be a challenge to apply in conventional power electronic circuit topologies. Take, for example, the half-bridge topology used in many applications today: if depletion mode fets are used as both the upper and lower switch, the gate control circuits must be operational, providing negative bias prior to attempting to power the dc bus. If not, the half-bridge would short across the bus if unbiased. Another option is to include a master enable switch that is not depletion mode – in series with the half-bridge – that would be enabled once the rest of the bridge circuit is ready to operate, but this adds cost and conduction loss. However, the design of the GaN HEMT can be adjusted to shift the gate threshold voltage from negative to positive, resulting in a normally off enhancement mode device. Enhancement mode GaN HEMTs are available up to 200V and are promised for 600V. But the convenience of enhancement mode must be balanced against a compromise in performance and robustness due to the challenges of gate drive implementation. Enhancement mode GaN HEMTs have a low threshold voltage and, typically, 1V between the full enhancement Vgs and the absolute maximum Vgs rating. Given the fast switching nature of GaN HEMTs, the gate drive circuit is susceptible to influences from 'gate bounce' due to C dv/dt coupling from drain to gate, and L di/dt voltage spikes resulting from fast current transitions in parasitic package and layout inductance. Nevertheless, enhancement mode GaN HEMTs offer some attractive figures of merit. Why cascode? The cascode connection of a GaN HEMT plus a 20 to 40V silicon fet is shown in figure 1. The cascode behaves much like a low voltage Si fet, with its operating voltage extended by the GaN HEMT. The GaN HEMT is connected to the silicon fet's drain and extends the range to 600V. Because the HEMT's gate is connected to its source, the silicon fet's Vds becomes the negative Vgs of the GaN HEMT, providing the necessary negative voltage bias for turn-off. This configuration helps to mitigate gate drive issues because the driven gate is the low voltage Si fet. While ;gate bounce' issues remain, the cascode's threshold and maximum gate voltages are much higher than an enhancement mode HEMT, with correspondingly reduced susceptibility.










The cascode GaN FET exhibits excellent body diode behaviour and this is one of the main features and advantages of 600V GaN cascode switches. Compared to igbts, superjunction or other Si FET alternatives, the reverse recovery charge (Qrr) of the GaN cascode is far superior (see fig 2). Measured Qrr is also nearly flat over temperature because, for a given Rds(on), Qrr in a 20 to 40V FET is several orders of magnitude less than that of a 600V FET Device capacitance and charge For hard-switched topologies, the FET output charge Qoss is dissipated each cycle, so Qoss is one of the components of frequency-dependent switching loss. A common switching loss figure of merit for FETs is therefore Rds(on) x Qoss – in other words, how much output capacitance related charge is lost each cycle for a given Rds(on). GaN cascode switches offer a performance about three times better than the best superjunction FETs and this ratio will continue to improve. There is sometimes confusion over the meaning of Qoss versus Qrr. Although these parameters are measured separately under different conditions, there is some overlap which can mask the true benefit of a technology like the GaN cascode. Reverse recovery charge Qrr is measured using a specialised half-bridge circuit known as a double-pulse tester: a body diode forward current is established in the upper FET, and then the lower FET turns-on, forcing a reverse recovery event in the upper body diode. The current is measured versus time and the overall reverse-conducting area is integrated, resulting in a value for Qrr. But imagine a perfect, ideal diode with some capacitance across it, evaluated in this way. The current required to discharge the capacitance appears as a negative and is integrated and called Qrr – but it is not real reverse-recovery charge (an ideal diode would have none), it is just capacitive charge. The point is that the traditional Qrr measurement lumps together true Qrr plus Qoss as one parameter called Qrr. This is important because different topologies are more sensitive to true Qrr and less to Qoss. As an example, a soft switching topology may incorporate Qoss into the overall resonant circuit, making it essentially lossless. But the delay and reverse current caused by diode recombination time related to true Qrr will result in power loss. The conclusion is that by just looking at single datasheet parameters or simple figures of merit may not tell the whole story. Each device needs to be evaluated carefully for its true losses in the application circuit. Gate charge is another parameter where GaN cascodes show significant benefit over Si FETs. Normalising again for Rds(on) by comparing Rds(on) x Qg under the same conditions, the GaN cascode exhibits a gate charge about eight times lower. Since gate charge is dissipated entirely by the gate drive circuit during charge and discharge each switching cycle, this reduction in Qg reduces the losses in the gate drive circuit directly, improving overall efficiency, especially at high frequencies. What makes GaN cascode more efficient? When diode function is required, a SiC Schottky has been used for best efficiency, while GaN enables topologies that require low Rds(on) and an excellent body diode – pushing applications into territories where traditional fets could not perform adequately. GaN cascode FETs have lower conduction loss than IGBTs, particularly at light load, and GaN can be operated in synchronous rectifier mode, reducing diode conduction loss compared to IGBTs. Compared to any silicon FETs – even with Fast Recovery Epitaxial Diodes (FREDFETs) – the GaN cascode has superior reverse recovery, enabling shorter transition times under hard switching conditions, reducing switching loss without increasing conducted EMI. The bottom line is that body diode behaviour limits the performance of all 600V switch options, because there is always the trade off between switching speed and EMI. In other words – you have to slow silicon FETs down – increasing switching loss – in order to pass conducted EMI. The first generation of GaN FETs being commercialised shows significant improvements over the best Si FETs available and the technology has a long and bright future ahead. Eric Persson is executive director of GaN applications and marketing with International Rectifier.