This type of cluster display is visually exciting, intuitively informative, easily configurable on-the-fly to display different types of data or image appropriately. The contrast with conventional electro-mechanical dials and gauges is stark. And thanks to the user-interface innovations of smartphones and tablets, today’s car buyers’ appreciation of the performance and appearance of the displays in the cabin is acute. The instrument cluster, in other words, has become an important marketing differentiator in premium vehicles.
The sophisticated graphics display-based instrument cluster has not found its way into the mainstream low-end and mid-range markets for new cars – at least, not yet. There is a very simple reason for this: cost. A graphics display such as that in the 2016 Audi TT, which contains no mechanical dials or gauges, calls for a large TFT LCD display, and an expensive chipset consisting of a high-end microcontroller with a separate high-performance graphics processor unit (GPU). The BoM cost for such a system is many multiples of the BoM cost of a conventional electro-mechanical cluster.
But if a manufacturer of a mid-range model could produce a more affordable variant of the high end graphics display in the instrument cluster, it could gain a real competitive edge. As a result automotive OEMs and tier one suppliers are developing variations on the theme of the ‘hybrid’ cluster with a high performance graphics display: typically this combines conventional electro-mechanical dials either side of a TFT LCD screen.
The advantage of this configuration is that the LCD screen can be much reduced in size and resolution compared to the all-electronic display in a high-end vehicle, providing a large BoM cost saving while still enabling the display of sophisticated 2D or 3D graphics. Information types such as mapping or parking assistance can be displayed impressively in 2D or 3D on a display measuring 3.5in diagonally.
This still, however, leaves the other large component of the system BoM cost of an all-graphics display: the chipset. To satisfy the BoM budget constraints of a mid-range vehicle, a single-chip solution for the entire instrument cluster is required – and this is where migration to the 40nm node has provided a breakthrough. The 40nm node has turned out to be a successful one for the semiconductor industry: yielding well, it is cost effective while providing great scope to integrate more or better features in a given die size.
And a single chip instrument cluster design requires a great deal of integration: it might include a high performance CPU, an LCD controller, high speed communications interfaces and multiple peripherals. Crucially, it also needs a large, high speed RAM, since memory capacity is a hard constraint on the display size and display resolution that a system can support.
Lifting memory density
An example of the potential for integration provided by the migration to the 40nm node is provided by the Traveo family of automotive microcontrollers from Cypress Semiconductor. Today’s 40nm Traveo devices offer up to 4Mbyte of embedded flash memory which operates at up to 80MHz without wait cycles, along with 384kbyte of SRAM. The 40nm MCUs also integrate an ARM Cortex-R5F core, which has an instruction and data cache operating at up to 240MHz and produces 400 DMIPS.
For many cluster designs, the memory embedded in the S6J33xx devices will be sufficient, helping the designer to minimise costs, power consumption and footprint. If even the 40nm devices’ embedded memory provision is not sufficient, however, the Traveo MCUs feature a HyperBus interface, which may be used to connect to external memory.
Figure 2: In the Traveo MCUs, the display controller and the LCD bus controller share the same pins
The current generation of HyperRAM and HyperFlash memories developed by Cypress offer a peak bandwidth of 200Mbyte/s over a 3V HyperBus interface, giving the user high speed operation while avoiding the high unit cost of DRAM parts.
Crucially, implementation of the Traveo platform design at 40nm allows integration of all the functions of a hybrid instrument cluster:
- Communication is provided by up to six channels of Controller Area Network-Flexible Data (CAN-FD) interfacing. An Ethernet AVB media access controller (MAC) enables the device to communicate with a vehicle’s networking backbone. There is also a multi-function serial interface with up to 12 channels.
- Security of the cluster’s data and signals is safeguarded by the IC’s Secure Hardware Extension (SHE), a secure zone within which the device performs key storage, AES-128 data encryption/decryption and random number generation.
- Driving the electro-mechanical elements of the cluster – the MCU includes six stepper motor controllers to run needles for the speedometer, rev counter etc.
- Audio sub-system – a 10-input sound mixer combined with a stereo audio DAC can generate a range of sophisticated sounds, and outputting them to the vehicle’s speakers over a two channel I2S interface. Cypress provides a sound authoring tool to support this function.
- LCD controller – the device can drive a TFT-LCD panel of 4 x 32 segments. The device provides a simple RGB888 video output.
- System control – the ARM Cortex-R5F core supports real-time operations and runs the Autosar 4.0.3 operating system. Real-time capability is crucial for safety-critical functions such as driving the speedometer needle.
This combination of capabilities makes the latest S6J33xx devices suitable for hybrid clusters with a small display: highly integrated, they enable designers to optimise the size and BoM cost of their system while providing for good-quality rendering of graphics encoded off-chip.
The MCUs also integrate an LCD bus controller. Combined with the display controller, this offers a low cost means to directly drive displays. The display sub-system’s integral plane has one layer with decompression support. Its fractional plane can combine up to eight layers with different sizes, colour formats and update rates. The eight layers themselves cannot be blended, but both planes can be alpha-blended. All layers can be stored in any memory, including external HyperFlash or HyperRAM memories.
Reading the available graphics from several sources, this allows a connected display to be driven without the need for a frame buffer, reducing the size of memory required to address any given display size or resolution.
Migration to the 40nm node, then, has enabled Cypress to substantially lift the level of integration of functions and capabilities in its Traveo series of automotive MCUs. In particular, the provision of up to 4MB of on-board Flash memory offers the potential for next generation hybrid clusters’ 2D graphics displays to operate without recourse to external memory, thus reducing the footprint, power consumption and BoM cost of the system. These next generation clusters will offer a user experience which has a feel similar to that of premium vehicles’ full free programmable clusters, but at a fraction of the BoM cost.
The use of a single-chip solution such as a S6J33xx MCU for these hybrid instrument clusters also streamlines the development process, since the operation of the entire cluster can be implemented within a single development environment supporting the MCU. What is more, other devices in the Traveo MCU family provide a migration path to higher-end hybrid clusters. The S6J327Cx series, for instance, integrates highly efficient 2D/3D graphics engines, and provides support for popular graphics development tools including CGI Studio and Altia Design.
The availability of multiple variants of the Traveo MCU platform allows manufacturers to modify a base cluster design to address the specifications for lower- or higher-end models, while using a single set of development tools.
As a result, manufacturers of low-end and mid-range vehicles have the opportunity to close the gap between the consumer appeal of old-style clusters and the sleek, attractive operation of an Audi TT-style cluster, at only a small BoM cost premium above that of the old-style instrument cluster.
Mathias Bräuer is director of product marketing at Cypress Semiconductor.