Engineering publications brought to you by Mark Allen

ASIC & SoC

Cadence achieves PCIe 5.0 specification compliance for PHY and Controller IP

New level translators support legacy and future mobile phone SIM cards

MediaTek announces the Dimensity 9000+

EW - Ryzen Embedded R-Series system-on-chips provide up to 2X more cores

Synopsys gives a boost to 5G SoC development with new RF design flow

Alchip Technologies offering 3nm ASIC design services

Avery Design Systems announces verification support for new UCIe standard

Cadence Design IP portfolio in TSMC’s N5 Process gains broad adoption

Preventing obsolescence with custom ICs

Top ten IC design company revenue tops $39 billion in 1Q22

Cadence accelerates SoC verification with expanded VIP and System VIP portfolio

Faraday launches Soteria! security IP subsystem for IoT ASIC