Engineering publications brought to you by Mark Allen

EDA & Design Software

Forget design for reuse; the new mantra is ‘build for change’

ARM, Altera collaborate on SoC design tools

Outlook 2013: Accelerating innovation and time to market

Chip design’s recycle cycle: Interview with Aart de Geus, chairman and co chief executive, Synopsys

How real number modelling is easing the analogue simulation challenge

Semiconductor R&D spending to hit record high in 2012

Cadence tests IP on TSMC’s 28nm processes

Improved interface speeds high frequency pcb design and analysis

Synopsys buys SpringSoft in $400million deal

SPICE simulator speeds analogue and rf designs

Cadence upgrades verification software

Balanced approach matches analogue design requirements