There are tensions that pull the engineering of real-time devices employing such technologies in different directions. Edge devices such as IoT sensor nodes and gateways call for the lowest-power operation. But this is not the only area that needs energy efficiency. Despite their reliance on high-performance graphics and responsiveness to movement, AR-enabled systems (such as head-up displays for machine operators) also have to preserve as much energy as possible, protecting battery life and preventing head-mounted displays from becoming uncomfortably warm. Similarly, versatile robots enabled by AI need to be able to operate away from mains power.
Distributed processing allows intensive computational work to be moved to the cloud and so offload the embedded systems. However, the real-time nature of these applications calls for low latency. Applications such as motion control and AR suffer if the delay from input to response is too long. This issue is leading to the deployment of edge computing server or ‘cloudlets’ - efficient server blades located relatively close to the edge devices themselves.
To support real-time applications such cloudlets are in a position to take advantage of changes in memory technology to better fit the real-time nature of the clients they serve than traditional server designs. Historically, engineers have been forced to choose between performance and persistence when designing bulk memories into real-time computer systems. DRAM is cost-effective for storing large amounts of data close to the processor but is volatile. To ensure data is not lost through power issues - which are more likely to occur in edge nodes - data often has to be copied to persistent storage, which have often much slower access times.
The move from rotating disk drives to flash memory for larger applications has already helped significantly when it comes to read access times. But flash still has its drawbacks when it comes to write performance. The erasing and rewriting of data from/to flash memory takes multiple cycles during which high-voltage pulses are delivered to the target memory cells. That takes both time and energy that system designers do not want to waste.
Next generation memory technologies are now appearing that overcome the write delays and power demands of flash. These technologies include ferroelectric memory, phase-change memory (PCM), magnetic random-access memory (MRAM) and resistive random-access memory (ReRAM). As devices based on these concepts become available, engineers can consider using them in novel memory hierarchies that optimise cost, increase resilience and improve real-time responsiveness.
PCM was first put forward as a possible memory material as long ago as the 1970s. It is based on the same group of chalcogenide materials as those used in rewritable optical disks. A useful feature of the chalcogenides is the way they react to heat. High-current pulses will melt the material. If left to cool quickly it turns to a resistive amorphous state. But the amorphous state can be converted to a crystalline form with a much higher conductivity by applying a small amount of heat. Thanks to this change in properties, readout circuitry can interpret the difference in resistivity between cells as representing ones and zeros.
Though similar in behaviour to PCM, with the same core approach of switching between high-resistance and low-resistance states, ReRAM uses different materials to chalcogenide. Typically, the movement of ions within the cell under the influence of pulses of current forms conductive filaments. Reset pulses disrupt these filaments, greatly increasing resistance. One potential advantage of ReRAM is that a large number of candidate materials could be chosen to implement them. This provides the scope for manufacturers to introduce memories with different levels of resilience and storage time.
Although these memories use current pulses, the total charge required to program a cell is much lower than that required for flash. In the memories being developed today, ReRAM requires less write energy than PCM but the write times are similar. However, endurance is better in PCM than ReRAM and PCM currently lies further ahead on the development path. Experts believe both PCM and ReRAM will scale better than flash in the long term and so could ultimately supplant flash entirely.
Ferroelectric memory and MRAM use the spin properties of electrons for storage. The spin can be controlled with very little energy through a spin-valve structure similar to that used in high-density read heads for magnetic disks. In an MRAM, this spin valve is made from a sandwich of materials formed in a via that lies between two metal interconnect lines on the surface of an integrated circuit (IC). The valve alters the resistance of the via based on the spin states of different materials in the sandwich.
Ferroelectric memory has been available for several decades but in comparatively low densities to those envisaged for the resistance-based memories. Ferroelectric memory requires both a capacitor and transistor to be formed on the base layer of the wafer. The other memories are all formed in the metal interconnect layers and, potentially, can be stacked for higher integration.
A key advantage for ferroelectric memory is its use of materials that polarise in two different directions based on an applied electric field. This polarisation requires even less power than is needed for MRAM, which makes it suitable for systems that need to be highly energy efficient.
A potential problem for all the novel memories today is that they lack the cost-effectiveness and density of flash, which is now beginning to take advantage of 3D manufacturing techniques. In reality, for cloudlets and also edge devices themselves, the density is not a major issue as these memories can serve as the underpinning for persistent caches.
The low-power and relatively fast write times of the novel memories provides applications with the ability to copy important data to the persistent cache. Data objects that need to be stored permanently can, from there, be copied to flash or disk storage. However, there is no longer any need to transfer data to flash or disk storage continually just to ensure that important but transient data is not lost. When the system restarts, it can recover its state from combining data in both the permanent and persistent arrays.
As costs come down and performance improves, there is the potential for MRAM, PCM or ReRAM to begin to displace DRAM and so move the architecture to one in which only the caches on the processors themselves employ a volatile memory architecture (such as SRAM).
Persistent memory technologies need not be isolated to cloudlets and high-performance systems. The use of ferroelectric memory by Texas Instruments in its MSP430 line of microcontrollers provides an example of the impact it can have in IoT edge nodes such as sensors. Many IoT applications will rely on energy harvesting to at least supplement a built-in battery. Some may dispense with the battery altogether.
The problem with energy harvesting is one of reliability. There are situations, such as vibrational energy capture on heavily used industrial machinery, where the power source is predictable. But in many cases, even with the use of a supercapacitor for an energy reservoir, the system may run temporarily short of power and need to shut down. When enough external energy is supplied, it can resume normal duties.
The use of ferroelectric technology provides the microcontroller with the ability to ensure data persists through unexpected power outages without incurring an energy penalty even when data is written to it frequently.
Although applications area, such as the IoT, AI and AR, will radically change real-time system architectures, new memory technologies will be able to address these demands accordingly. Through the development of MRAM, PCM, ReRAM and ferroelectric memories it will be possible for system designs to support the responsiveness and cost-effectiveness required.