Industry groups collaborate to create 3d chip technology infrastructure
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Sematech, the Semiconductor Industry Association (SIA) and Semiconductor Research (SRC) have established the 3D Enablement programme in a move designed to create the infrastructure necessary for the industry to take advantage of 3d packaging technology for innovative new applications.
Faced with the increasing technical challenges of scaling to follow Moore's Law, the industry is looking with more interest at 3d chips. Sematech says that, while research into 3d technologies has been underway for many years, the approach has not achieved mainstream production due to lack of uniform standards and a limited understanding of key manufacturing parameters.
The programme, launched by a group of SIA and Sematech members, will focus on developing technologies and specifications in critical areas such as inspection, metrology, microbumping, bonding and thin wafer and die handling. SRC will help to select suitable university research projects.
"This initiative underscores the importance of industry wide convergence on infrastructure and standards," said Dan Armbrust, pictured, Sematech's president and ceo. "The 3D Enablement programme has been established to bring down the barriers to integrating chips from different suppliers for adoption of 3d technologies in high volume manufacturing."
"The semiconductor industry – specifically the development of 3d integration – is at an inflection point," said Dr John Kelly, senior vice president and director of research at IBM and chair of SIA's technology steering committee. "We will have deep collaboration with Sematech and SRC, addressing bonding processes and 3d inspection."
