Self repairing chips still function while degrading

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Researchers at the European consortium, Cutting Edge Reconfigurable Ics For Stream Processing (CRISP) have demonstrated a self testing and self repairing chip which they claim can test cores and connections, with a resource manager dynamically assigning the chip's tasks to fault free parts.

"Because of the rapidly growing transistor density on chips, it has become a real challenge to ensure high system dependability," said Hans Kerkhoff, Associate Professor, CTIT, University of Twente. "To address the question of how to make sure future miniature chips become more reliable instead of less robust, we decided to research how chips can test and repair themselves." According to Kerkhoff, the technology combines a test for faulty components and connections on chips with a run time resource manager which assigns tasks and communication channels to known good components and pathways. This allows many core chips with some faulty cores to pass production test because they are able to function without any compromise to reliability. "The solution is not to make non degradable chips, it is to make architectures that can degrade while they keep functioning, which we call graceful degradation," said Kerkhoff. "With the right dependability infrastructure, many cores can be a solution." The Professor added that the chips have many cores, with each core able to perform subtasks of a more complex application. "A run time resource manager dynamically determines which core does which task and it doesn't make a difference which core does what, so cores can take over the tasks from failing cores and the chip can repair itself, extending its longevity." According to Prof Kerkhoff, the resource manager works during the entire chip lifetime to keep the chip up and running. "Its primary function is to dynamically assign new tasks to free resources and this allows us to truly benefit from the huge processing power of many cores and creates a much desired flexibility to adapt to new tasks and standards during the functional life of the chip."