Process changes point to cheaper, better finFETs

The manufacturing techniques chosen by FinScale are designed to overcome problems in device performance caused by the tradeoffs made by manufacturers such as Intel to improve yield. Previous experimental devices made in a number of fabs employed a rectangular shape. But Intel and others found that it was difficult to pattern the gate and coat the fins with insulating oxide at the base to help isolate them from each other without resorting to the triangular cross-section. FinScale CEO Jeff Wolf said its approach would allow chipmakers to go back to the rectangular shape, which would in turn allow the fins to be both thinner and packed together more tightly as processes scale. One problem with current processes is that 'the fins end up standing alone after the etching process', said Wolf. "In our process, the fin never stands alone." CTO Victor Koldyaev said a key element of the process is the way in which the fin is formed within fields of shallow trench isolation (STI) oxide, rather than depositing the STI after fin construction, which is the conventional technique. He claimed the FinScale approach would provide straighter sides, higher aspect ratios and lower surface roughness, whilst using a technology that is available in every fab. "STI etch is a fundamental industry process," he said. STI etch has been proposed by other manufacturers for defining the central section of a fin that is then grown in the slot between oxide regions, but FinScale has taken the approach of etching the fin out of the silicon substrate itself. According to Wolf, FinScale's approach makes it possible to build the fins without resorting to the double patterning techniques needed for existing finFET processes. "The 2D self aligned process allows you to build the fin with only one litho step. We have device designs and process integration recipes," Wolf claimed. However, the company has yet to make test chips. "The performance should be very good, but we have yet to experiment," said Koldyaev. "People ask how I can be sure that the interface will be good. We have some proprietary knowledge that is not widely known in the industry on quantum effects." Although FinScale uses the name quantum finFET or qfinFET to refer to its design, the structure does not work any differently to a conventional finFET. The name is derived from simulation work performed by Koldyaev to determine the minimum possible size of a silicon finFET using quantum mechanical techniques. The 3.5nm thickness derived by Koldyaev pointed to a minimum useful channel length of 10nm for silicon. Wolf said: "We built a structure around that and found we could move it backwards. We have detailed designs at 22nm, 14/16nm and we are now working on 28/32nm, to help those processes live forever. We open up a lot of degrees of freedom." Although experiments have indicated that rectangular fins should perform better with undoped silicon, manufacturers are finding ways to exploit the triangular cross-section, not only to overcome its issues but also to improve on fundamental finFET performance. At the recent Design Automation Conference, Professor Chenming Hu of UC Berkeley – who devised the first finFET structure – said: "A surface that is not vertical can potentially provide higher mobility." TSMC, for example, has worked on techniques that allow it to deposit silicon with crystal orientations that improve carrier mobility on top of a deliberately angled fin. "There are various reasons people want to play with the structures. It's not going to be one fixed structure for the finFET," said Prof Hu.