Researchers have therefore been working on techniques to reduce the contact resistance on highly doped n-Silicon and p-SiliconGermanium (p-SiGe) source/drain contacts, aiming for values below 10^-9Ω.cm².
At the 2017 Symposia on VLSI Technology and Circuits, imec reported record breaking values below 10^-9Ω.cm² for PMOS source/drain contact resistivity. These results were obtained through shallow gallium implantation on p-SiGe source/drain contacts with pulsed nanosecond laser anneal.
“This breakthrough achievement in our search to develop solutions for next generation deeply-scaled CMOS provides a possible path for further performance improvement using the current source/drain schemes in 5nm and 7nm nodes,” commented Naoto Horiguchi, distinguished member of the technical staff at imec.
imec researchers added a high dose of gallium or boron into SiGe separate wafers and applied various anneal processes. They then fabricated multi-ring circular transmission line model structures, which are highly sensitive to contact resistance.
This process causes a gallium doped germanium surface segregation, which is responsible for the ultralow sub-10^-9Ω.cm² contact resistivity.
