"For integrating graphene into advanced silicon microelectronics, large-area graphene free of wrinkles, tears and residues must be deposited on silicon wafers at low temperatures, which cannot be achieved with conventional graphene synthesis techniques," said Professor Jihyun Kim. "Our work shows the carbon ion implantation technique has great potential for the direct synthesis of wafer-scale graphene for integrated circuit technologies."
Although chemical vapour deposition is widely used for the large-area synthesis of graphene on copper and nickel films, this approach is not suited for silicon microelectronics, because temperatures in excess of 1000°C are needed and the graphene then has to be transferred to the silicon.
"The transferred graphene often contains cracks, wrinkles and contaminants," said Prof Kim. "Thus, we are motivated to develop a transfer-free method to directly synthesise high quality, multilayer graphene in silicon microelectronics."
In the new approach, carbon ions were accelerated onto a layered surface made of nickel, silicon dioxide and silicon at a temperature of 500°C, with the nickel layer used as a catalyst for graphene synthesis. The process was then followed by high temperature activation annealing to form a honeycomb lattice of carbon atoms.
According to Prof Kim, the ion implantation technique offers finer control on the final structure of the product than other fabrication methods, as the graphene layer thickness can be precisely determined by controlling the dose of carbon ion implantation.
"Our synthesis method is controllable and scalable, allowing us to obtain graphene as large as the size of a silicon wafer," Prof Kim said.
The next step for the team is to further lower the temperature in the synthesis process and to control the thickness of the graphene for manufacturing production.