Hybrid memory cube interface spec finalised
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A meeting of more than 100 members of the Hybrid Memory Cube Consortium has agreed the final interface specification for the technology. According to the consortium, a major breakthrough has come with the use of advanced technologies to combine high performance logic with state of the art dram.
"The consensus we have among major memory companies and many others in the industry will contribute significantly to the launch of this promising technology," said Jim Elliott, Samsung's vice president, memory planning and product marketing. "As a result of the work of the HMCC, IT system designers and manufacturers will be able to get new green memory solutions that outperform other memory options offered today."
One of the primary challenges facing the industry is that memory bandwidth has increased beyond what conventional memory architectures can efficiently provide. The HMC is clamed to bring increased density and bandwidth with significantly lower power consumption.
The specification provides an advanced, short reach (SR) and ultra short reach (USR) interconnection across physical layers (PHY) for applications requiring tightly coupled or close-proximity memory support for fpgas, asics and assps.
SR is designed for applications needing channel lengths of up to 8in, while USR is targeted at very short and power efficient channels with lengths from 1 to 2in. SR PHYs will be aimed at 100G and 400G systems that require high bandwidth memory buffering. USR PHYs, meanwhile, are said to consume just 2pJ/bit.
The consortium's next goal is to advance standards designed to increase data rate speeds from 10, 12.5 and 15Gbit/s to 28Gbit/s for SR and from 10Gbit/s to 15Gbit/s for USR.
