So what is P1687 – and what benefits will it bring to the design community? Al Crouch, chief technologist at ASSET InterTech and contributor to the P1687 working group, outlined the standard: "IEEE P1687 is a standard that specifies an access network architecture and a description language for embedded instruments.
"The standard's hardware description enables the development of an architecture with which engineers can achieve their design budgets and tradeoffs. The power of the standard, though, is that the operations of embedded instruments can be described in the P1687 Procedure Description Language (PDL), which makes the embedded instrument portable. The access network itself is documented in P1687's Instrument Connectivity Language (ICL), which allows test automation tools to retarget the PDL to the chip's interface."
Bassilios Petrakis, product marketing director for Digital Design and Verification at Cadence, added: "P1687 is a standardisation effort to allow SoC designers to integrate instrumentation included in any third party IP cores that they use along with instrumentation in their own IP, and to provide a formal documentation of all the embedded instrumentation to their SoC vendor, test vendor and, ultimately, their SoC user."
The foundation for IJTAG lies in IEEE1149.1 – more commonly known as Boundary Scan. However, boundary scan is a standard that is largely intended for testing interconnections – whether they be inside a chip, chip to board or chip to chip. However, it has features that offered further possibilities, as Crouch explained: "It was coopted by designers as a method to access and control embedded test and debug instruments because the four or five boundary scan pins on a chip would remain accessible after the chip was packaged. The main complaint was that the use of 1149.1 by designers for non board test purposes caused problems. The 1149.1 standard was not optimised for use with hundreds or thousands of embedded instruments, leading to non ideal architectures.
"In addition, using 1149.1 with many embedded instruments added excess material, like long instruction registers and extra material to Boundary Scan Description (BSDL) files, making its use for board test less than ideal.
"The recent update to 1149.1 (1149.1-2013) addressed much of this, but it did not change the fact that boundary scan is still based on instructions and registers (Test Data Registers, or TDRs). 1149.1's equivalent of the PDL is written to the TDR, not to the embedded instrument, which limited an instrument's portability."
Having the new standard, designed specifically for the management and coordination of embedded instruments, should not be more of a drain on system resources, according to Petrakis: "The embedded instrumentation normally already exists in the chip internal logic for debug, bring-up or functional or system test use. What P1687 provides is a standardised access method as an alternative to a proprietary test bus that is usually deployed. In most cases, P1687 should not require any more chip resources than a proprietary solution."
IJTAG benefits
In fact the focus becomes on 'retargeting' resources that already exist to yield a number of benefits: "First," Crouch continued, "it creates an on-chip standardised method to access and operate instruments, whether they are for test, debug, yield-analysis, environmental monitoring or functional configuration. Formerly, separate and distinct access methods were used for each of these purposes.
"In addition, P1687 makes access to on-chip embedded instruments more efficient and scalable, especially as the number of instruments grows. In contrast, legacy access methods, such as instruction based access methods, can require thousands, or millions, of instructions. P1687 also allows concurrent operation of multiple instruments and flexible instrument scheduling.
"And, lastly, the P1687 standard makes instruments portable, insofar as they can be placed anywhere in an on-chip network or can be replicated multiple times in a network. In both of these cases, the instrument's operations are simply retargeted by automated software tools."
As mentioned before, the P1687 Working Group was diverse in its interests, which may have made the formulation process a lengthy one, but this has resulted in a standard that has had to meet the needs of many. Its impact will consequently be felt across the entire lifecycle of a circuit, as Crouch describes. "P1687 will need an ecosystem that spans the entire chip and board lifecycle. An embedded instrument's IP will likely be delivered with an ICL description of its pins and a PDL description of its operations.
This instrument IP can then be integrated into a chip and either eda tools or designers will then create the access network. In the end, the instrument and the on-chip network might be adjusted to meet engineering tradeoffs, like power, routing congestion, area, size, access time, frequency of operation and length of scan path. At the chip level, the P1687 network, ICL and PDL can be used for design verification and for test. Next, these same constructs can be applied in board and system debug, validation and test. The result is that the board test developer receives a component that includes files (BSDL, ICL, PDL) that allow operation of the component's public features. Some of those features include memory test, serdes adjustments and component configuration that would help the board designer."
Cadence is one of the EDA companies to which users will turn to for advice about how to design effectively using P1687, but Petrakis does not predict much upheaval as a consequence. "Most likely, the SoC integrator – as well as the end user – may have to retool their software to take advantage of the standard. It covers a vast landscape, so users may pick and choose parts of the standard that they benefit from the most and requires the least retooling and migrate slowly."
IJTAG has already been creeping into circulation. It subsumes both traditional 1149.1 TDR-based architectures and those based on IEEE1500, while adding several new architectural techniques. Converting existing architectures into P1687 often only requires documenting the embedded instruments with PDL and describing the access network with ICL. Crouch noted: "After doing this, eda tools for retargeting the vectors can be brought to bear. The use of P1687 retargeting tools has been evident publicly since at least 2010. More recently, the eda design tools companies have been publicly pushing IJTAG insertion and verification and ic test generation. Also, a good many of the companies represented on the working group are chip providers who have already promoted having P1687 architectures on their chips."
Conclusion
A broad range of embedded instruments, which are available for many different purposes and which can be used in many different niches, can now all be accessed in a standard manner by a standard architecture and described in standard languages. This creates many benefits for the industry: plug and play instruments and instrument networks; portable instruments; and the automated retargeting of vectors and procedures.
Crouch concluded: "P1687 may also prove critical to new 3d chip designs, where the embedded content of the devices and their limited vertical access creates more pressing challenges with regards to access, scheduling and power management."
