A breakthrough amplifier design features extremely low noise levels.
When the first monolithic operational amplifier – Fairchild's µA702 – was introduced in 1963, its noise performance was not specified. And noise performance remained relatively unimportant until the late 1980s, when a few amplifiers were introduced that offered an input voltage noise approaching 1nV/vHz. Since then, no company has taken amplifier noise performance to the next level, in spite of customer demand and improvements in process technology. During this time, however, significant advances have been made in sensor technology for applications such as ultrasound, sonar and radar. For example, today's leading edge non ceramic, single crystal transducers have much greater sensitivity and larger gain than previous examples and this requires an amplifier with the lowest noise possible in order to maximise the system's overall performance. There is a handful of amplifiers on the market that offer noise performances of better than 1nV/vHz – figures for noise density generally range from 0.9 to 0.92 or 0.94 – but there is only one that offers 0.85nV/vHz. The CLC1001 amplifier from Cadeka moves beyond this arbitrary noise benchmark and sets the standard for the industry's next generation of low noise amplifiers. Using a proprietary architecture to improve the noise/power tradeoff, the CLC1001 can deliver 0.6nV/vHz noise without increasing the quiescent current to values greater than found in competing devices that offer 1nV/vHz. Until now, many applications have been forced to sacrifice performance in order to save power. The CLC1001 is a high performance voltage feedback amplifier with ultra low input voltage noise. The CLC1001 provides a gain-bandwidth product of 2.1GHz and a slew rate of 410V/µs. This makes the device suitable for use in high speed data acquisition systems with high sensitivity and signal integrity requirements. The amplifier also offers low input offset voltage. The CLC1001 is designed to operate from a supply ranging from 4 to 12V and consumes 12.5mA per channel. A power saving pin disables the amplifier and decreases the supply current to less than 225µA. The amplifier operates over the extended temperature range of -40 to 125°C. Making full use of the low noise of the CLC1001 requires careful consideration of resistor values. The feedback and gain set resistors and the non inverting source impedance all contribute noise to the circuit and can easily dominate the overall noise if their values are too high. The datasheet is specified with a gain set resistor of 22.1O, at which point the noise from Rf and Rg is about equal to the noise from the CLC1001. Lower value resistors could be used at the expense of more distortion. However, the CLC1001 is not the first product from Cadeka to set a new industry standard: the CDK8307 is another groundbreaker (see figure 1). This 12bit a/d converter with lvds consumes only 50mW per channel at 65Msample/s. It's possible that this converter family may well start a new era in ultra low power a/d converter products. The core design is based on a technique where, through an analytical approach, a physical optimum is found for biasing any given analogue configuration. This design technique is unprecedented in the market and, when combined with a proprietary pipeline architecture and 0.18µm cmos process technology, results in the market's most power efficient converters. Cadeka claims this architecture is superior to any other when it comes to the power/performance ratio. Figure 2 illustrates the power consumption and signal to noise ratio for the CDK8307 compared to several competing products. Power is not the device's only industry leading feature. Targeted predominantly at portable ultrasound applications, the CDK8307 offers designers reduced startup times. This allows significant power reductions to be achieved in duty cycled systems through the use of the sleep mode or the power down mode when the receive path is idle. The CDK8307 also employs internal reference circuitry, eliminating the need for external decoupling, lowering part count and saving board space. Various modes and configuration settings can be applied to the a/d converter through the serial control interface. Each channel can be powered down inde¬pendently and data format can be selected through this interface. A full chip idle mode can be set by a single external pin and the exact function of this pin can be determined by register settings. Performance is not sacrificed, with the device boasting a signal to noise ratio of 72.2dB and a spurious free dynamic range of 71.5dB. The CDK8307 is an eight channel cmos a/d converter. The 13bits supplied by each channel are serialised to 12, 13 or 14bits and sent out on a single pair of pins in LVDS format. All eight channels operate from a single differential or single ended clock. The sam¬pling clocks for each of the eight channels are generated from the clock input using a carefully matched clock buf¬fer tree. The 12x/13x/14x clock required for the serialiser is generated internally from FCLK using a phase locked loop (PLL). A 6x/6.5x/7x and 1x clock are output in lvds format, along with the data to enable easy data capture. The CDK8307 uses internally generated references that can be shorted across several devices to improve gain matching. The differential reference value is 1V, resulting in a differential input of -1V, to correspond to the zero code of the a/d converter, and a differential input of +1V to correspond to the full scale code. The a/d converter employs a pipelined converter architecture. Each stage feeds its output data into the digital error correction logic, ensuring good differential linearity and no missing codes at 13bit level. The CDK8307 operates from two sets of supplies and grounds: the analogue supply and ground set; and the digital set. Four variants are available: with sample rates of 20, 40, 50 and 65Msample/s. Meanwhile, the CDK8307, which requires a 1.8V supply, is designed to interface readily with fpgas from leading vendors. Deep analogue roots Although the company name is relatively new, Cadeka's heritage extends back to the late 1980s, when many of its engineering staff began working together at Comlinear. This former supplier of leading high performance amplifier products was acquired by National Semiconductor in 1995. Comlinear is where the team discovered its passion for amplifiers and analogue technology, focusing on high performance amplifiers and data converters targeted at high end applications. Since the Comlinear years, the team's experience has grown through three separate company transitions, including assignments at: National Semiconductor, Kota Microcircuits and, most recently, Fairchild Semiconductor. Many of Cadeka's analogue designers and engineers have worked together for 23 years. During this period, their focus has moved from developing the highest performance amplifiers and converters that carried a similarly high price tag to developing amplifiers and converters designed for best performance in their respective applications, but at competitive prices. According to ceo Gary Ross: "Our focus is on providing cost effective, leading edge analogue products and solutions. We are amplifier experts and are passionate about being successful with our core competency."