Exposing EUV continuing uncertainties
1 min read
TSMC is not planning to use extreme ultraviolet (EUV) lithography at the 10nm node, according to co ceo Dr Mark Liu's response to a question at its recent financial analysts meeting.
EUV is the preferred lithographic solution for advanced processes because its wavelength of 13.5nm is 'there or thereabouts' when it comes to feature size. Immersion lithography – the current approach – relies on 193nm light being 'squashed' by exotic liquids. The industry originally expected EUV to enter the production flow at the 32nm node, but 'technical issues' continue to push it back. Significantly, EUV developers still haven't created light sources powerful enough to provide the wafer throughput that manufacturers require. That means wafers will continue to be exposed using immersion lithography, but ever smaller features will require triple – even quadruple – patterning, making it an increasingly expensive process, with associated yield issues. The parlous state of EUV development was recognised in 2012 when Intel, Samsung and TSMC all invested in equipment manufacturer ASML in an attempt to get things moving. Yet it seems to be as far off as it has always been, although ASML's acquisition of light source specialist Cymer appears to have kicked things on a bit. ASML's president and chief executive officer Peter Wennink said in October 2013 the company 'remained on target' to achieve a throughput of 125 wafers an hour in 2015. He believed EUV has the 'potential' to be inserted at the 10nm node – which could be as early as 2015 or as late as 2022, depending on how you define it. Manufacturers such as TSMC would be beyond happy if EUV arrived in time for the 10nm node, where it should make it less expensive to make chips. But don't hold your breath.